Row-Buffer Memory Controller for Open-Row Access Scheduling
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Solution Overview
Problem
Existing DRAM memory systems suffer from inefficiencies due to asymmetric access times between open and closed rows, leading to suboptimal utilization of the memory bus.
Innovation Solution
A memory controller that prioritizes memory access requests to open rows and row buffers, leveraging a command queue and arbiter to schedule operations that maximize the use of row-buffer memory, allowing simultaneous access to multiple rows within a bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access requests are processed in order without prioritization, then the memory system operates with simple control logic, but memory bus efficiency is reduced due to repeated precharge and activation overhead
Solution Approach 1:
The memory controller pre-fetches data from memory rows into page buffers before they are needed, and pre-charges rows in advance. This preliminary action allows the controller to have data ready and rows prepared, eliminating wait states and improving memory bus efficiency without requiring complex real-time arbitration logic.
Solution Approach 2:
The memory controller maintains multiple page buffers that can be accessed continuously while memory rows are being precharged or activated. By keeping page buffers populated with data and allowing continuous access to them, the controller eliminates idle time on the memory bus and maintains productive action throughout the memory access cycle.
2Speed
If the memory controller waits for complete row activation before processing access requests, then access timing is simplified, but access speed deteriorates due to inability to overlap operations
Solution Approach 1:
The memory controller activates memory rows and transfers data to page buffers in advance of when the data is actually needed. This preliminary row activation and data transfer allows subsequent read requests to be serviced immediately from the page buffer without waiting for memory access, thereby increasing access speed while using simple buffer management logic.
Solution Approach 2:
The invention introduces a temporal dimension to memory access by overlapping row activation, data transfer, and request processing operations in time. Multiple operations proceed simultaneously in different time phases, allowing the controller to service requests faster without requiring complex interlocking control logic for each operation sequence.
3Loss of time
If page buffers are closed immediately after use, then buffer management is simplified, but subsequent accesses to the same row require full re-activation causing time loss
Solution Approach 1:
The memory controller pre-charges memory rows and maintains them in a precharged state before they are needed for subsequent accesses. This preliminary precharging action ensures that when a row needs to be accessed again, it is already prepared and can be activated quickly without the full precharge delay, reducing time loss while using simple state-maintenance logic.
Solution Approach 2:
The memory controller keeps page buffers and memory rows in an active or precharged state continuously rather than closing them immediately. By maintaining this continuous ready state, the controller enables rapid successive accesses to the same or related rows without interruption, improving time efficiency with minimal additional control complexity.
Data Source
AI summary
A memory controller includes a command queue and an arbiter. The command queue is operable to store a plurality of memory access requests for accessing a row-buffer memory. The arbiter is coupled to the command queue and is operable to pick memory access requests from the command queue for issuance to the row-buffer memory according to a preference for memory access requests that access a data element in a sense amplifier or in a first row buffer of the row-buffer memory.