Memory Bank Row Buffer Pairing for Dual-Path PIM MAC Throughput
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Solution Overview
Problem
Existing memory systems face inefficiencies in performing multiply and accumulate operations due to the need for multiple address inputs and limited utilization of operators, leading to suboptimal performance in computing tasks like convolutional neural networks.
Innovation Solution
The memory device incorporates a memory bank with a row buffer and selecting module that allows for simultaneous transmission of two operands through independent data paths to a PIM block, utilizing sub-column addresses to pair data for simultaneous operation, and includes multiplexers to control data flow and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CNN operations are executed using general-purpose processors, then the device complexity is reduced, but the computing efficiency deteriorates due to the large number of MAC operations required
Solution Approach 1:
The patent merges the memory function and processing function into a single integrated structure. The memory device includes memory cells for storing operands and an operation module for performing MAC operations directly within the memory device, eliminating the need for separate general-purpose processors and improving computing efficiency through functional integration.
Solution Approach 2:
The patent introduces a dedicated operation module as an intermediary between memory storage and external processing units. This operation module performs MAC operations on data stored in memory cells, serving as a mediator that bridges the gap between simple memory storage and complex external processing, thereby improving computing efficiency without requiring complex external processors.
2Device complexity
If data is transferred externally for processing, then the memory device structure is simplified, but the bandwidth utilization deteriorates due to the need for external data transfer
Solution Approach 1:
The patent combines memory storage and processing operations within the same device structure. The operation module is integrated with the memory cells, allowing MAC operations to be performed on data without external transfer. This merging eliminates the need for complex external processing infrastructure while maximizing bandwidth utilization by keeping data within the memory device.
3Device complexity
If multiple operations are performed sequentially, then the device complexity is reduced, but the processing time increases due to the considerable amount of computation required
Solution Approach 1:
The patent segments the processing function into a dedicated operation module that is integrated with the memory structure. This operation module is specifically designed to perform MAC operations, dividing the complex processing task from simple memory storage. This segmentation allows parallel operation of storage and processing, reducing processing time without requiring overly complex device architecture.
Solution Approach 2:
The patent performs preliminary action by pre-loading operand data into memory cells before the MAC operation is executed. The operation module then performs computations on this pre-positioned data, eliminating the need for sequential data fetching and processing. This preliminary positioning of data enables faster execution and reduces overall processing time.
Data Source
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AI summary
A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.