Row Decode Circuitry for NAND Flash Memory Access
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Solution Overview
Problem
Current memory access operations in NAND flash memory systems face challenges in achieving faster access times due to limitations in row decode circuitry, leading to inefficiencies in decoding memory access addresses.
Innovation Solution
The implementation of a novel row decode circuitry configuration that uses a single block decoding circuitry to manage multiple blocks of memory cells, employing nFETs and pFETs to optimize voltage levels and reduce power consumption by minimizing the need for high voltage levels during access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional row decode circuitry is used in NAND flash memory, then memory access operations can be performed, but access speed is limited and power consumption increases
Solution Approach 1:
The patent combines multiple block decoding functions into a single shared block decoding circuitry unit. Instead of having separate decoding circuits for each block, one decoding unit services multiple blocks by time-multiplexing its operations. This consolidation reduces the total number of decoding circuits, lowering power consumption while maintaining the ability to access any block in the memory array at high speed through efficient resource sharing.
Solution Approach 2:
The block decoding circuitry is designed as a universal unit that can decode addresses for any block in the memory array. Rather than being dedicated to a single block, the decoding circuitry performs multiple functions by serving different blocks at different times. This multi-functional approach allows the same hardware resources to be reused across multiple blocks, reducing overall power consumption while preserving fast access capabilities.
2Productivity
If multiple separate block decoding circuitries are used, then each block can be accessed independently, but device complexity and power consumption increase
Solution Approach 1:
The patent merges multiple separate block decoding circuitries into a single shared decoding unit. This consolidation reduces device complexity by eliminating redundant decoding circuits while maintaining memory access efficiency through time-multiplexed operation. The single decoding unit alternates between serving different blocks, providing the functional equivalent of multiple independent decoders with fewer physical components.
Solution Approach 2:
The patent segments the memory array into multiple blocks that can be independently accessed, while the decoding function itself is consolidated. The memory structure is divided into blocks for independent addressing and access, but the decoding circuitry that enables this block-level independence is shared rather than duplicated. This segmentation of memory with shared control logic achieves both independence and complexity reduction.
Data Source
AI summary
Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, with each driver circuitry connected to a respective block of memory cells.