Row Decoder Stabilization for Memory Address Bus
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Solution Overview
Problem
Existing row decoders in memory devices face issues with incorrect word line selection due to asynchronous address management and propagation delays, leading to temporary unpredicted values in the address bus, which can result in data loss during writing operations.
Innovation Solution
A semiconductor memory device with a row decoder that includes row selection units with enabling devices, which are activated only after a predetermined time from receiving the row address, ensuring that the address bus stabilizes before word line selection, thereby preventing incorrect selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If row selection units are immediately activated upon receiving the row address, then the word line selection responds quickly, but incorrect word lines may be selected due to unstable address bus values during transition
Solution Approach 1:
The enabling device is activated in advance before the row selection unit processes the address, creating a time window that ensures address stability. The enabling device receives the row address and activates the row selection unit only after a predetermined time has elapsed, allowing the address bus to stabilize first. This preliminary timing control prevents incorrect word line selection while maintaining efficient operation.
2Reliability
If the row decoder waits for address stabilization before activation, then correct word line selection is ensured, but the operation speed decreases
Solution Approach 1:
The system performs the stabilization wait within the enabling device's activation timing rather than as a separate delay step. The enabling device is configured to activate the row selection unit after a predetermined time from receiving the row address, which incorporates the stabilization requirement into the normal operation flow without adding external delays.
3Device complexity
If asynchronous address management is used to simplify control logic, then device complexity is reduced, but propagation delays cause unpredictable address bus values
Solution Approach 1:
The enabling device incorporates a predetermined time delay mechanism that allows asynchronous address bits to stabilize before the row selection unit processes them. This timing-based approach maintains the simplicity of asynchronous control logic while ensuring address stability, avoiding the need for complex synchronization circuits.
Data Source
AI summary
A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address.