Row Decoder Area Reduction via Custom Logic Stages
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Solution Overview
Problem
Existing row decoders for non-volatile memory devices, such as flash memory, occupy a large area, which is a limitation in applications where size reduction is necessary, such as portable devices.
Innovation Solution
The row decoder is optimized by implementing custom logic-combination stages with a reduced number of transistors, specifically using three MOS transistors instead of six, to generate decoded address signals while maintaining the same logic OR operation, thereby reducing the area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic-combination stages with six transistors are used, then reliable logic OR operation is achieved, but the area occupation increases
Solution Approach 1:
The patent merges the functions of multiple transistors into customized logic-combination stages. Specifically, it combines the OR logic function with voltage boosting functionality, eliminating the need for separate six-transistor stages while maintaining reliable logic operation. The customized stages integrate multiple functions into fewer components, reducing area occupation.
Solution Approach 2:
The patent changes the transistor count parameter from the conventional six transistors per logic-combination stage to three transistors per customized stage. This parameter change is achieved through careful circuit design that maintains logical equivalence while reducing component count, directly addressing the area occupation issue.
2Adaptability or versatility
If more transistors are used in logic-combination stages, then logic functionality is enhanced, but the decoding speed decreases
Solution Approach 1:
The patent extracts and eliminates unnecessary transistors from the conventional six-transistor logic-combination stages, retaining only the essential three transistors needed for the OR logic function combined with voltage boosting. This extraction of redundant components reduces the propagation delay and increases decoding speed while maintaining necessary logic functionality.
3Adaptability or versatility
If conventional row decoder configuration is used, then complete address decoding is achieved, but the area occupation is large
Solution Approach 1:
The patent makes the logic-combination stages multi-functional by integrating both the OR logic operation and voltage boosting functions into a single customized stage. Each three-transistor stage performs multiple functions that would traditionally require separate circuits, thereby reducing the overall area occupation while maintaining complete address decoding capability.
Data Source
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AI summary
A row decoder (38), for a non-volatile memory device (1), has: an input and pre-decoding module (10, 12, 14), which receives address signals (ASr) and generates pre-decoded address signals (PASHV); a decoding module (40) which receives the pre-decoded address signals (PASHV), for generation on an output (out) of decoded address signals (DASHV) having a high or low value; and a driving module (18), which generates biasing signals (S_WL) for biasing wordlines (WL) of a memory array (2). The decoding module (40) envisages a plurality of decoding stages (42), each of which is designed for carrying out an operation of OR logic combination between a first predecoded address signal to be combined (psxhvn) and a second predecoded address signal to be combined (sxyhv) and is provided with: at least one first pass transistor (45a), for selectively transferring onto the output (out) the value of one between the first and second predecoded address signals to be combined, in at least one first operating condition; and at least one first pull-up transistor (46a), designed to selectively bring the output (out) to the high state, in at least one second operating condition.