Row Decoder Array Architecture for 3D NAND Chip Size Reduction
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Solution Overview
Problem
The increasing demand for high-capacity and high-integration memory devices, particularly in 3D NAND flash memory, leads to a challenge in reducing chip size due to the need for taller row decoders that match the height of memory blocks, resulting in increased chip size.
Innovation Solution
The implementation of a memory device with a row decoder array architecture that includes a peripheral circuit structure and a cell array structure, where the cell array is divided into normal and dummy memory blocks, allowing for shared row decoder circuits and through-electrodes to reduce the overall height of the row decoder, thereby minimizing chip size without adding additional memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the row decoder height is increased to match the memory block height in 3D NAND flash memory, then the memory device can support higher capacity and integration, but the chip size increases
Solution Approach 1:
The memory device is divided into a peripheral circuit structure and a cell array structure that are vertically overlapped. The row decoder is segmented into multiple unit row decoders (first unit row decoder, second unit row decoder, etc.) that are arranged in different vertical layers. This segmentation allows the row decoder to control multiple memory blocks without requiring the entire decoder to span the full memory block height, thereby reducing chip size while maintaining high capacity.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking architecture. The cell array structure is positioned vertically above the peripheral circuit structure, with word lines extending in the vertical direction. This dimensional change allows the row decoder to be distributed across multiple vertical layers rather than requiring a large horizontal area, effectively reducing chip size while supporting high-capacity memory blocks.
2Device complexity
If additional memory blocks are added to fit the row decoder height, then the row decoder can be properly sized, but the chip size increases
Solution Approach 1:
Multiple unit row decoders are designed with identical or similar structures, where each unit row decoder can control a specific number of memory blocks (e.g., first unit row decoder controls 3 memory blocks, second unit row decoder controls 2 memory blocks). This universality allows the same decoder design to be replicated and reused across different vertical positions, simplifying the overall device complexity while avoiding the need to add extra memory blocks merely to accommodate decoder height requirements.
Solution Approach 2:
Different unit row decoders are assigned to control different numbers of memory blocks based on their vertical positions. For example, the first unit row decoder controls 3 memory blocks while the second unit row decoder controls 2 memory blocks. This local differentiation optimizes the decoder configuration for each specific region without requiring uniform addition of memory blocks throughout, thereby preventing unnecessary chip size increase.
Data Source
AI summary
A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.