Row Decoder Circuit Bulk Voltage Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing row decoder circuits are not suitable for selectively applying high negative voltages to deselected word lines during the depletion verify step in flash memories, leading to increased area occupation due to the need for level shifters, which complicates the operation and increases the size of the circuit.
Innovation Solution
The proposed solution exploits the bulk effect to modulate the threshold voltage of transistors in the row decoder circuit by applying progressive negative voltages to the bulk terminals, allowing for the selective application of high negative voltages to memory cells without increasing the circuit area, using a biasing device to generate and apply these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level shifters are introduced into the row decoder circuit to generate high negative voltage for depletion verify, then the ability to selectively apply high negative voltage to deselected cells is improved, but the area occupation of the row decoder circuit increases substantially
Solution Approach 1:
The patent extracts the high negative voltage generation function from the row decoder circuit by using a separate charge pump circuit. The row decoder only needs to control the timing and selection, while the charge pump independently generates the required high negative voltage, eliminating the need for level shifters within the row decoder structure.
Solution Approach 2:
The patent introduces a charge pump circuit as an intermediary component that mediates between the standard voltage supply and the memory cells requiring high negative voltage. This intermediary handles the voltage conversion externally, allowing the row decoder to maintain its original compact structure while still achieving the required voltage levels for depletion verify.
2Reliability
If level shifters are integrated in the pitch of the cells to generate high negative voltage, then the high negative voltage application is achieved, but the area occupation of the memory array increases
Solution Approach 1:
The patent removes the voltage conversion function from the memory array pitch by placing the charge pump circuit outside the array. This extraction allows the memory cells to maintain their original compact layout without accommodating additional level shifter components within the cell pitch.
Solution Approach 2:
The patent moves the voltage generation function to a different spatial dimension - from within the two-dimensional cell pitch to an external circuit located in the periphery or separate layer. This dimensional relocation preserves the compactness of the memory array while achieving the required voltage levels through externally located charge pump circuitry.
3Device complexity
If known row decoder circuits are used without bulk effect exploitation, then the circuit structure is simpler, but the selective application of high negative voltage to deselected cells is not achieved
Solution Approach 1:
The patent changes the voltage parameter applied to the bulk terminals of the transistors to achieve selective control. By applying negative voltage to the bulk terminals during depletion verify, the transistor threshold voltages are modified, enabling selective interdiction of deselected cells while maintaining simple circuit structure.
Solution Approach 2:
The patent makes the existing row decoder transistors serve a dual function by exploiting the bulk effect. The same transistors that perform row selection also provide selective interdiction when negative bulk voltage is applied, eliminating the need for separate level shifter circuits and maintaining structural simplicity while achieving selective high negative voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the correct execution of the depletion verify step on cells in a deep depletion state without substantially increasing the area occupation of the row decoder circuit, ensuring proper interdiction of deselected cells while maintaining compatibility with existing control logic.
Implementation Method 1
The proposed solution exploits the bulk effect to modulate the threshold voltage of transistors in the row decoder circuit by applying progressive negative voltages to the bulk terminals
Data Source
AI summary
A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.