Row Decoder Circuit Using Cascode Transistors for High Voltage
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Solution Overview
Problem
Existing row decoder circuits in non-volatile memories require high-voltage rating transistors, which increase manufacturing costs and occupy larger areas due to thick gate oxides.
Innovation Solution
A row decoder circuit design that uses only low-voltage rating transistors (up to 2.5 V) to manage high voltages (up to 5 V) by employing a specific configuration of cascode and selection transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage rating transistors are used to handle high voltages (0 V to 5 V), then the row decoder can operate correctly with high supply voltages, but the transistors require thick gate oxides and large area occupation, increasing manufacturing costs
Solution Approach 1:
The patent divides the voltage handling function into multiple stages: a first stage handles voltages up to 2.5 V using standard low-voltage transistors, while a second stage handles voltages from 2.5 V to 5 V using additional transistors. This segmentation allows each transistor to operate within its safe voltage rating, eliminating the need for expensive high-voltage rating transistors while maintaining the ability to handle high supply voltages.
Solution Approach 2:
The patent introduces an intermediary voltage level (2.5 V) that acts as a threshold between two operating modes. By using this intermediate voltage level, the circuit can transition between using low-voltage transistors for normal operation and activating additional transistors for high-voltage operation, thereby avoiding the need for dedicated high-voltage rating transistors throughout the circuit.
2Reliability
If high-voltage rating transistors are used to handle high voltages (0 V to 5 V), then the row decoder can operate correctly with high supply voltages, but the transistors require thick gate oxides and large area occupation
Solution Approach 1:
The patent segments the transistor population into two groups: a first plurality of transistors for low-voltage operation (0 V to 2.5 V) and a second plurality of transistors for high-voltage operation (2.5 V to 5 V). This segmentation allows the circuit to use compact low-voltage transistors for most operations and only deploy additional transistors when high voltage is required, minimizing overall area occupation compared to using high-voltage rating transistors for all operations.
Solution Approach 2:
The patent implements a dynamic transistor activation mechanism where the second plurality of transistors is activated only when the supply voltage exceeds 2.5 V. This dynamic behavior allows the circuit to adapt its transistor configuration based on the operating voltage, using fewer transistors during normal operation and only expanding when necessary, thereby reducing average area occupation.
3Reliability
If high-voltage rating transistors are used to handle high voltages (0 V to 5 V), then the row decoder can operate correctly with high supply voltages, but dedicated manufacturing steps and masks are required, increasing manufacturing complexity
Solution Approach 1:
The patent segments the transistor functionality into two distinct groups with different voltage ratings, allowing each group to be optimized for its specific voltage range. This segmentation enables the use of standard low-voltage transistor manufacturing processes for the first plurality of transistors, while the second plurality of transistors can be integrated using conventional high-voltage transistor fabrication techniques, avoiding the need for entirely dedicated manufacturing steps and masks.
Solution Approach 2:
The patent utilizes parameter changes in transistor threshold voltages and operating conditions to differentiate between low-voltage and high-voltage transistor behavior. By carefully selecting transistor parameters and operating voltage ranges, the circuit achieves high-voltage handling capability using a combination of standard and high-voltage transistors, thereby reducing the need for dedicated manufacturing processes.
Data Source
Figure 1
Figure 2~3
AI summary
In a row decoder circuit (10') an input node receives a row selection signal (ln_lv) and an output node is coupled to a word line (WL) of a memory device. A pull-down circuit (12a) coupled between the word line (WL) and a ground node (GND) at ground voltage selectively couples the word line to the ground node in response to the row selection signal (ln_lv) being asserted. A pull-up circuit (14) coupled between the word line and a supply node (15) that provides a selectable supply voltage (shifted_supply) selectively couples the word line to the supply node in response to a deselection signal (Vcomm) being de-asserted. An inverter circuit (16) supplied between the supply node and a shifted ground node (17) that provides a selectable reference voltage (shifted_gnd) receives as input a control signal (V1) from a control node (18) and produces the deselection signal. A current generator (19) sources a biasing current (I1) to the control node. A further pull-down circuit (121b, 122b, 300, 12xb, 12b') coupled between the control node and the ground node selectively couples the control node to the ground node in response to the row selection signal being asserted. The further pull-down circuit (12b') comprises a first cascode n-channel transistor (121b), a cascode p-channel transistor (300), a second cascode n-channel transistor (122b), and at least one selection transistor (12xb) having their conductive channels arranged in series between the control node and the ground node, wherein the selection transistor is controlled by the row selection signal.