Row Decoder Global Line Layout for Compact Memory Arrays
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Solution Overview
Problem
Current memory devices face challenges in reducing size and failure, particularly in the disposition of global lines which complicates the placement of coupling lines without increasing device size.
Innovation Solution
The memory device is designed with a substrate having a first and second cell region and a row decoder region, featuring a plurality of pass transistors, bottom and top wiring layers, and global lines that transfer operating voltages, with the global lines only in the bottom wiring layer to avoid size increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If global lines are disposed in both bottom and top wiring layers, then coupling lines can be disposed more flexibly, but the memory device size increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple wiring layers (bottom and top) to provide additional routing paths for global lines. This allows coupling lines to be disposed in alternative locations without increasing the planar footprint of the memory device, effectively resolving the contradiction between routing flexibility and device size.
2Ease of manufacture
If more wiring layers are added to accommodate global lines, then coupling line placement becomes easier, but device complexity increases
Solution Approach 1:
The patent segments the wiring structure into distinct bottom and top wiring layers, each serving specific routing functions. This segmentation allows coupling lines to be placed in the top layer while global lines are routed in the bottom layer, simplifying the manufacturing process by providing clear separation of functions rather than requiring complex multi-layer interconnections.
Data Source
AI summary
A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.