Row Decoder Level Conversion to Reduce NBTI in 3D NAND
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Solution Overview
Problem
The degradation of electrical performance in level conversion circuits due to large voltage differences in memory devices, particularly in three-dimensional NAND memory systems, leads to a reduced service life and increased Negative Bias Temperature Instability (NBTI) in transistors.
Innovation Solution
Implementing a row decoder with a low level select circuit and a level conversion circuit that alternates between different control signals to reduce the voltage difference across transistors, thereby mitigating NBTI effects and extending the service life of the level conversion circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level conversion circuit is used to convert voltage levels in a memory device, then voltage level conversion is achieved, but large voltage differences cause NBTI degradation and reduce transistor service life
Solution Approach 1:
The patent applies periodic action by alternating between a first control signal and a second control signal with different voltage levels. The level conversion circuit periodically switches between these control signals, causing the transistor to alternately experience different voltage stress conditions. This periodic alternation prevents continuous exposure to large voltage differences, thereby reducing cumulative NBTI degradation and extending transistor service life while maintaining voltage level conversion functionality.
2Power
If large voltage differences are applied for level conversion, then voltage level conversion is achieved, but transistor performance degrades due to NBTI effects
Solution Approach 1:
The patent implements periodic action by using alternating control signals with different voltage characteristics. The transistor experiences periodic variations in voltage stress rather than continuous large voltage differences. This allows the level conversion circuit to maintain its voltage conversion capability while reducing the cumulative electrical stress that causes NBTI degradation, thus preserving transistor electrical performance over time.
Solution Approach 2:
The patent applies parameter changes by varying the control signal parameters (voltage level, timing) dynamically. Instead of using a fixed control signal with large voltage difference, the circuit switches between multiple control signals with different voltage levels and timing characteristics. This dynamic parameter adjustment enables the level conversion to achieve the required voltage transformation while modulating the voltage stress on the transistor to minimize NBTI effects.
Data Source
AI summary
A memory device includes a peripheral circuit and a memory array coupled with the peripheral circuit. The memory array includes at least one memory block. The peripheral circuit includes at least one row decoder. One memory block is correspondingly connected with one row decoder. The row decoder includes a logic circuit and a level conversion circuit. The logic circuit is configured to generate a first control signal, a second control signal, and a first output signal based on an address signal and a status signal of the memory block correspondingly connected with the row decoder. A level of the second control signal is higher than a level of the first control signal. The level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.