Row Decoder NOR Logic Layout for Smaller DRAM Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for higher integration and larger capacity in memory devices, particularly DRAM, necessitates a reduction in chip size, which is predominantly dependent on the area occupied by the core peripheral circuit region, especially the row decoder.
Innovation Solution
A memory device with a row decoder circuit that includes a main word line driver circuit and a sub-word line driver circuit, utilizing NOR logic circuits to generate and activate word line driving signals based on row address signals, thereby reducing the area occupied by the row decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory device uses a conventional row decoder structure, then the decoding function is achieved, but the chip size is large due to the area occupied by the core peripheral circuit region
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where the cell array structure is positioned above the core peripheral circuit structure. This vertical stacking enables the row decoder to be integrated beneath the memory cell array, utilizing the space underneath and significantly reducing the overall chip footprint while maintaining full decoding functionality.
Solution Approach 2:
The row decoder circuit is nested within the overall memory device structure by placing it in the core peripheral circuit structure that supports the cell array structure. The bonding metal pads and interlayer insulation layers create a nested configuration where the row decoder operates in the lower layer while the memory cell array occupies the upper layer, effectively hiding the decoder within the device's vertical architecture.
2Quantity of substance
If the memory device increases integration density, then storage capacity improves, but the circuit operation delay time increases due to more complex wiring structures
Solution Approach 1:
By moving to a three-dimensional stacked architecture, the patent reduces the horizontal distance between the row decoder and the memory cell array. The vertical connection through bonding metal pads and via electrodes shortens the signal path compared to planar layouts, thereby reducing circuit operation delay time while enabling higher integration density and storage capacity.
Solution Approach 2:
The patent divides the memory device into distinct functional layers: the core peripheral circuit structure containing the row decoder in the lower layer, and the cell array structure with memory cells in the upper layer. This segmentation allows each layer to be optimized independently for its specific function while reducing inter-layer interference and signal transmission delays through vertical interconnects.
Data Source
AI summary
A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.