Row Decoder Design Eliminates High Voltage PMOS for Memory Size Reduction

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Solution Overview

Problem

Existing row decoders in semiconductor memory devices require a large size due to the use of high voltage transistors, which increases the size of the memory device, especially when handling high voltage operations for programming or erasing.

Innovation Solution

A row decoder design that includes a decoding and precharging unit with high voltage n-type metal oxide semiconductor (NMOS) transistors and a pass transistor block, which decodes addresses and transmits row driving voltages to row lines without using high voltage p-type metal oxide semiconductor (PMOS) transistors, reducing the overall size by eliminating the need for a large PMOS transistor area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage p-type metal oxide semiconductor (PMOS) transistors are used in the row decoder, then the ability to handle high voltage operations is improved, but the size of the row decoder increases

Engineering Contradiction:

Improvehigh voltage operation capabilityVSAvoidrow decoder size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the high voltage PMOS transistor from the row decoder structure, extracting the problematic component that causes size increase while maintaining high voltage operation capability through alternative means

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The decoding transistor is designed to perform multiple functions: it decodes address signals and simultaneously serves as a switch for high voltage transmission, eliminating the need for separate dedicated high voltage PMOS transistors

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If high voltage transistors are used to switch high voltage for program or erase operations, then the capability to perform memory operations is improved, but the size of the row decoder increases

Engineering Contradiction:

Improvememory operation capabilityVSAvoidrow decoder size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The decoding transistor serves dual purposes: it performs address decoding and simultaneously acts as a high voltage switch, enabling the same component to handle both control and power switching functions

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the decoding function and high voltage switching function into a single transistor component, combining what were previously separate functions into one integrated element

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9818483B2Row decoder and a memory device having the same

Publication Date: 2017.11.14 SAMSUNG ELECTRONICS CO LTD

AI summary

A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.