Row Decoder Pull-Up Stage Low-Voltage Control
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Solution Overview
Problem
Existing row decoders for non-volatile memory devices require high-voltage signals for selection and deselection, leading to increased current consumption and access time during reading and writing operations.
Innovation Solution
A row decoder design that uses low-voltage signals to control pull-up stages, eliminating the need for high-voltage signals and level shifting, and incorporates a control circuit with a local mirror transistor, cascode transistors, and selection transistors to manage word line voltage during selection and deselection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage signals are used for row decoder operation, then word line selection and deselection can be achieved, but current consumption increases
Solution Approach 1:
The patent changes the voltage parameter from high-voltage operation to low-voltage operation by introducing a voltage conversion mechanism. The row decoder is designed to operate with low-voltage decoded address signals, and a voltage conversion circuit transforms these low-voltage signals into the appropriate voltage levels for controlling the access elements, thereby reducing current consumption while maintaining reliable word line selection.
Solution Approach 2:
The patent introduces an intermediary voltage conversion mechanism between the low-voltage decoded address signals and the high-voltage word line control signals. This intermediary circuit converts the low-voltage selection signals into the necessary voltage levels for driving the word lines and access elements, allowing the row decoder itself to operate at low voltage while still achieving high-voltage control where needed.
2Reliability
If high-voltage signals are used for row decoder operation, then word line selection can be achieved, but access time increases
Solution Approach 1:
The patent changes the voltage parameter from high-voltage operation to low-voltage operation throughout the row decoder circuitry. By operating the decoder logic and control circuits at low voltage, the switching speeds are improved due to reduced RC time constants and faster charge/discharge cycles, thereby reducing access time while maintaining reliable word line selection through the voltage conversion mechanism.
3Use of energy by moving object
If low-voltage signals are used for row decoder operation, then current consumption is reduced, but voltage level conversion is required
Solution Approach 1:
The patent introduces a voltage conversion circuit as an intermediary component that transforms low-voltage decoded address signals into the appropriate voltage levels for controlling access elements and word lines. This intermediary mechanism allows the main row decoder logic to operate at low voltage (reducing current consumption) while still providing the necessary high-voltage control signals through the conversion circuit.
4Reliability
If traditional row decoder design is used, then high-voltage control is achieved, but level shifting is required
Solution Approach 1:
The patent changes the operating voltage parameter of the row decoder from high-voltage to low-voltage operation. The decoder logic and control circuits are designed to operate at low voltage levels, eliminating the need for level shifting within the decoder itself. A voltage conversion circuit then transforms these low-voltage control signals into the appropriate high-voltage levels for driving the word lines and access elements, thereby maintaining high-voltage control capability while reducing the need for level shifting circuitry in the main decoder path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces current consumption and access time by operating with low-voltage signals, improving the efficiency of word line selection and deselection processes in non-volatile memory devices.
Implementation Method 1
a control circuit (199) generating a control signal (Vcomm)<n> making it possible to raise the voltage of the word lines (WL)<n>
Implementation Method 2
a local mirror transistor (200), whose source terminal is set at said supply voltage (VDD), said drain terminal of which forms an internal node (INT)
Implementation Method 3
a first cascode transistor (202) and a second cascode transistor (204), both of which are N-channel enhancement MOSFETs, a first selection transistor (206), a second selection transistor (208) and a third selection transistor (210)
Implementation Method 4
an inverter circuit (212) generating, on the basis of the voltage present on said internal node (INT), an output signal (Vcomm)<n> applied to the gate terminal of the deselection transistor (126R)
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A non-volatile memory device (100) including an array (102A_R) of memory cells (3), coupled to word lines (WL_dx), and a row decoder (105) including a pull-down stage (110L, 110R) and a pull-up stage (118), which includes, for each word line (WL_dx): a corresponding control circuit (199), which generates a corresponding control signal (Vcomm<n>); and a corresponding pull-up switch circuit (122R, 126R), which is controlled via the control signal (Vcomm<n>) so as to couple/decouple the word line (WL_dx) to/from the supply (VDD). The control circuit (199) includes: a current mirror (200,300), which injects a current (11) into an internal node (INT); and a series circuit (202,204,206,208,210), which couples/decouples the corresponding internal node (INT) to/from ground, on the basis of selection/deselection of the corresponding word line (WL_dx) so as to cause a decrease/increase in a voltage on the corresponding internal node (INT). Each control signal (Vcomm<n>) is a function of the voltage on the corresponding internal node (INT).