Row Decoder Resistance Mismatch for Memory RC Delay

Solution Overview

Problem

In nonvolatile memory devices, the variation in resistance values of wiring lines connected to signal lines leads to deviations in setup time and RC delays, affecting the efficient application of driving voltages, especially as the number of word lines increases and spacing between wiring lines narrows.

Innovation Solution

The implementation of nonvolatile memory devices with first and second row decoders, each having pass transistors connected to signal lines with different resistance values at opposing ends, reducing the deviation in setup time and RC delays by optimizing the resistance values of wiring lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If wiring lines are narrowed to increase the number of word lines, then memory capacity increases, but resistance variation and RC delay deviation worsen

Engineering Contradiction:

Improvenumber of word linesVSAvoidsetup time deviation

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the wiring lines have different resistance values at different locations. Specifically, the first wiring line connected to the first row decoder has a first resistance value, while the second wiring line connected to the second row decoder has a second resistance value that is different from the first. This local variation in resistance compensates for the RC delay differences caused by narrowed wiring spacing, thereby reducing setup time deviation without sacrificing memory capacity.

Inventive Principle:

Principle #3Local quality

2Quantity of substance

If wiring lines are narrowed to increase the number of word lines, then memory capacity increases, but RC delay variation worsens

Engineering Contradiction:

Improvenumber of word linesVSAvoidRC delay deviation

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by making the wiring lines have different resistance values at different locations. Specifically, the first wiring line connected to the first row decoder has a first resistance value, while the second wiring line connected to the second row decoder has a second resistance value that is different from the first. This local variation in resistance compensates for the RC delay differences caused by narrowed wiring spacing, thereby reducing setup time deviation without sacrificing memory capacity.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies parameter changes by deliberately varying the resistance values of different wiring lines. The first wiring line has a first resistance value and the second wiring line has a second resistance value, which are different parameters designed to compensate for RC delay variations. By changing the resistance parameter of specific wiring lines, the patent optimizes the overall signal propagation characteristics across the memory device.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If row decoders are added to provide driving voltage at both ends, then voltage application efficiency improves, but device complexity increases

Engineering Contradiction:

Improvevoltage application efficiencyVSAvoidnumber of row decoders

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the row decoding function into two separate row decoders (first row decoder and second row decoder) positioned at opposite ends of the memory cell array. Each row decoder independently provides driving voltage to its respective side, allowing simultaneous voltage application across the entire array. This segmentation improves voltage application efficiency by reducing the distance voltage must travel through high-impedance nodes, despite increasing the number of decoder components.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the deviation in setup time and RC delays between signal lines, ensuring more predictable and efficient application of driving voltages, thereby improving the performance of nonvolatile memory devices.

Implementation Method 1

a first wiring line having a first resistance value and the second wiring line having a second resistance value different from the first resistance value

Methodology Applied

Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11437088B2Memory device including row decoders

Publication Date: 2022.09.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.