Row Decoder Wiring Architecture for 3D Memory Area Reduction
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Solution Overview
Problem
Three-dimensional memory devices face increased size and manufacturing costs due to the need for more electrode layers and pass transistors, leading to a wiring line bottleneck that expands the device area.
Innovation Solution
A memory device design with slimming regions on both sides of the row decoder and distributed wiring lines that couple pad parts of row lines and the row decoder, reducing the number of wiring lines and preventing the wiring line bottleneck, thereby maintaining a compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode layers is increased to increase the degree of integration, then the storage capacity is improved, but the number of pass transistors and wiring lines increases, causing the device area to expand
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where memory cells are arranged vertically across multiple layers. The row decoder is positioned in a separate layer beneath the memory cell array, allowing wiring lines to route in the horizontal plane while electrode layers stack vertically. This dimensional separation enables increased integration capacity without proportionally increasing the footprint area.
Solution Approach 2:
The memory device is divided into distinct functional layers: a memory cell array layer containing electrode layers and bit lines, and a separate row decoder layer positioned beneath. This segmentation allows independent optimization of each layer's wiring and component layout, reducing overall device area by eliminating the need for extensive wiring in a single plane.
2Quantity of substance
If fine patterning processes are used to narrow line width for high integration, then the storage density is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent changes the architectural parameters from planar to three-dimensional stacking, achieving high storage density without requiring extreme fine patterning. By increasing the number of stacked electrode layers rather than narrowing line widths, the design attains high integration using conventional fabrication capabilities, thereby reducing manufacturing costs.
3Adaptability or versatility
If the number of wiring lines coupling the row decoder and electrode layers is increased, then the connectivity is improved, but the area consumed for wiring line layout increases
Solution Approach 1:
The row decoder is placed in a separate layer beneath the memory cell array, creating a three-dimensional wiring architecture. Wiring lines route horizontally in the row decoder layer to connect to vertical vias that access electrode layers above, enabling high connectivity with minimized planar wiring area.
Solution Approach 2:
Vertical vias serve as intermediary connection elements between the row decoder layer and the electrode layers above. These vias enable compact three-dimensional routing, allowing wiring lines to connect across layers without consuming excessive horizontal space.
Data Source
AI summary
A memory device includes a memory cell array included in a first semiconductor layer, and including a plurality of row lines that extend in a first direction, each of the plurality of row lines having a pad part disposed in a slimming region; a row decoder included in a second semiconductor layer disposed under the first semiconductor layer, and overlapping the memory cell array in a vertical direction; slimming regions disposed on both sides of the row decoder in the first direction; and a plurality of wiring lines coupling the pad parts of the plurality of row lines and the row decoder.