Row Decoder Circuit for Rapid Word Line Leakage Detection
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Solution Overview
Problem
Dynamic memory devices, such as DRAM, suffer from defects in word lines due to manufacturing issues, leading to leakage currents that increase standby power and cause malfunctions, and existing methods are inefficient in detecting and repairing these defects.
Innovation Solution
A row decoder circuit with a power supply node, transistors, and a comparator that performs a defect test on multiple word lines by pre-charging, developing, and sensing voltage differences to quickly identify defective lines, allowing for rapid detection and repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential defect testing methods are used, then device complexity is reduced, but detection time increases significantly
Solution Approach 1:
The patent divides the word lines into multiple groups and uses a binary search approach to systematically test each group. The row decoder circuit is segmented into multiple test circuits, each responsible for a specific group of word lines. This segmentation allows parallel testing of multiple word lines simultaneously, reducing detection time from O(n) to O(log n) complexity.
Solution Approach 2:
The patent merges multiple testing functions into a single integrated row decoder circuit that can simultaneously test multiple word line groups. The circuit combines pre-charging, development, and sensing operations across multiple parallel test circuits, enabling concurrent defect detection in multiple word lines without requiring separate testing sequences for each line.
2Productivity
If all word lines are tested simultaneously, then detection speed increases, but circuit complexity and power consumption increase
Solution Approach 1:
The patent segments the testing process into multiple stages: pre-charging stage where all word lines are charged, development stage where test circuits are activated, and sensing stage where voltage differences are detected. Within each stage, the circuit is divided into multiple parallel test circuits, each handling a specific group of word lines. This segmentation enables simultaneous testing while managing complexity through staged operation.
Solution Approach 2:
The patent employs periodic action by cycling through multiple testing stages (pre-charging, development, sensing) in a sequential manner. Each stage prepares the circuit for the next, allowing efficient reuse of test circuits. This periodic operation enables high productivity by continuously testing different word line groups without requiring all circuits to be active simultaneously.
3Reliability
If defective word lines are not detected quickly, then manufacturing defects increase, but detection time increases
Solution Approach 1:
The patent performs preliminary pre-charging of all word lines to a known voltage state before the actual defect testing begins. This preliminary action ensures that all word lines start from a consistent electrical state, making the subsequent defect detection more reliable and time-efficient. The pre-charging stage prepares the testing circuitry in advance, reducing the overall detection time while maintaining high reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the sensing circuitry continuously monitors voltage differences between test circuits and compares them against reference values. When a voltage difference exceeds a threshold, the system immediately identifies the defective word line and can stop testing or alert the control circuit. This feedback enables rapid defect detection while maintaining high reliability through continuous monitoring and immediate response.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables rapid detection and repair of defective word lines, reducing detection time complexity and ensuring normal device operation by using a binary search technique to pinpoint defects, thus improving device reliability and efficiency.
Implementation Method 1
in a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the plurality of third transistors are turned off, so that the first node and the plurality of second nodes are charged
Implementation Method 2
a comparator configured to output a detection signal based on a first voltage of the first node and a reference voltage
Implementation Method 3
in a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the plurality of second nodes is discharged at a different rate depending on whether a current of a first respective corresponding word line is leaked
Data Source
AI summary
A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged. In a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the second nodes is discharged at a different rate depending on whether current of the corresponding word line is leaked, and in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to voltage levels of the discharged second nodes.