Row Decoding Circuit Leakage Reduction via Reference Signal Control
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Solution Overview
Problem
Row decoders in memory devices experience significant power consumption due to sub-threshold leakage, gate direct tunneling leakage, and gate-induced drain leakage, which are not effectively mitigated by existing designs.
Innovation Solution
A row decoding circuit with a plurality of row decoding blocks, each comprising a row decoder that includes an inverter, a selecting transistor, and switch transistors, where a high-level first reference signal is provided when a high voltage row selecting signal is output, reducing sub-threshold leakage and leveraging high-level second control signals to minimize gate direct tunneling and gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional row decoders are used with multiple transistors, then the row decoding function is achieved, but sub-threshold leakage, gate direct tunneling leakage and gate induce drain leakage occur increasing power consumption
Solution Approach 1:
The patent changes the voltage level parameter of the reference signal from low to high. Specifically, when the selecting transistor is turned on, the first reference signal is set to a high voltage level instead of a low voltage level. This parameter change reduces the voltage difference across the switch transistors, thereby suppressing sub-threshold leakage and reducing power consumption while maintaining the row decoding function
Solution Approach 2:
The patent applies equipotentiality by setting the first reference signal to a high voltage level that matches the system high voltage. This reduces the potential difference across the switch transistors when they are in the off state, minimizing leakage currents caused by sub-threshold effects, gate direct tunneling, and gate induce drain leakage
2Loss of energy
If more transistors are added to reduce leakage, then leakage suppression is improved, but the area of the circuit increases
Solution Approach 1:
Instead of adding more transistors to reduce leakage, the patent changes the operating voltage parameter of the existing circuit. By setting the first reference signal to a high voltage level, the patent achieves leakage reduction through parameter optimization rather than structural expansion, thereby avoiding increased circuit area while still suppressing sub-threshold leakage and gate-induced drain leakage
Data Source
AI summary
A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders. Each of the row decoders receives a pre-charge signal, and includes an inverter, a selecting transistor and at least one switch transistors. The inverter receives the corresponding pre-charge signal, and outputs a first control signal. The first source/drain of the selecting transistor is coupled to a system high voltage, the gate receives the first control signal, and the second source/drain outputs a corresponding row selecting signal to a memory array of a memory device. The switch transistors are coupled between the second source/drain of the selecting transistor and a corresponding first reference signal in series. When the selecting transistor is controlled by the first control signal and turned on, the first reference signal is set to a high voltage level.