Row Hammer Control Block for Semiconductor Memory Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High integration density in semiconductor memory devices leads to the phenomenon of row hammering, which affects data reliability and security due to the proximity of word lines, causing changes in adjacent memory cells' data characteristics.

Innovation Solution

A semiconductor memory device with a row hammer control block that includes a victim word line determination circuit and a victim voltage output circuit, which applies a different voltage to a victim word line adjacent to a selected word line during its falling section to prevent data changes by moving trapped negative charges to adjacent memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integration degree is increased to improve memory density, then productivity is improved, but row hammering occurs causing data reliability to deteriorate

Engineering Contradiction:
Improvememory densityVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by detecting when an aggressor word line is activated and proactively applying a specific voltage to the victim word line before data corruption can occur. This preventive measure counteracts the row hammering effect by maintaining the victim word line's electrical state, thereby preserving data reliability while allowing high-density integration to continue

Inventive Principle:
Principle #9Preliminary anti-action

2Productivity

If pitch between word lines is reduced to improve integration density, then productivity is improved, but electrical interference between adjacent word lines increases causing row hammering

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary mechanism - a voltage control circuit that monitors aggressor word line activation and responds by applying a compensating voltage to the victim word line. This intermediary action mediates the electrical interference caused by reduced pitch, allowing high integration density while preventing harmful row hammering effects through active electrical compensation

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively mitigates row hammering by temporarily applying a victim voltage to the victim word line, improving data reliability and preventing data decay, thereby enhancing the security and reliability of semiconductor memory devices.

Implementation Method 1

applying a victim voltage different from an off voltage, which may be applied to non-selected word lines during a falling section of the aggressor word line... applying a victim voltage different from the off voltage to the victim word line during a falling section where a voltage of the selected word line is changed from the driving voltage to the off voltage

Methodology Applied
Scientific EffectElectrical charge movement: Electrical Impedance Tomography

Data Source

PatentUS20250022502A1Semiconductor memory device capable of controlling row hammering and method of driving the same
Publication Date: 2025.01.16 SK HYNIX INC
  • US20250022502A1 patent drawing
  • US20250022502A1 patent drawing
  • US20250022502A1 patent drawing

AI summary

A semiconductor memory device may include a memory cell array and a row hammer control block. The memory cell array may include word lines, bit lines crossed with the word lines and memory cells arranged between the word lines and the bit lines. The row hammer control block controls a voltage of a victim word line adjacent to a selected word line among the word lines, and includes a victim word line determination circuit and a victim voltage output circuit. The victim word line determination circuit receives address information of the selected word line as address information of an aggressor word line to determine at least one of the word lines adjacent to the aggressor word line. The victim voltage output circuit may temporarily output a victim voltage different from an off voltage, which is applied to non-selected word lines during a falling section of the aggressor word line.