Row Hammer Detection Circuit with Hybrid Sampling
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Solution Overview
Problem
Conventional DRAM devices face data corruption due to 'row hammer' effects, where frequent access to one row of memory accelerates data loss in adjacent rows, and sophisticated attacks can evade detection by existing row hammer detection circuitry.
Innovation Solution
A semiconductor device with a refresh control circuit incorporating hybrid and act-based sampling circuits, which generate randomized sampling signals to detect and mitigate row hammer attacks by differentiating between normal and accelerated refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row hammer detection circuitry is used, then simple row hammer attacks can be detected, but sophisticated decoy attacks using higher frequencies can evade detection
Solution Approach 1:
The patent changes the frequency parameter of row hammer attacks by introducing decoy attacks at higher frequencies to mask the targeted lower frequency attacks. This parameter variation allows attackers to evade conventional detection circuitry that operates at fixed frequencies, thereby reducing detection accuracy against sophisticated attacks.
2Reliability
If memory density is increased to meet high data reliability demands, then chip size is reduced, but row hammer effects accelerate data loss in adjacent rows
Solution Approach 1:
The patent implements preliminary anti-action by detecting row hammer attacks before they cause data corruption and proactively refreshing adjacent rows that are susceptible to accelerated data loss. The refresh control circuit identifies targeted rows through sampling circuits and initiates preventive refresh operations on neighboring rows, counteracting the harmful row hammer effect before data loss occurs.
3Reliability
If refresh operations are performed on adjacent rows to prevent data loss, then data retention is improved, but normal memory operations are disrupted
Solution Approach 1:
The patent employs feedback mechanisms where sampling circuits continuously monitor memory access patterns and provide information to the refresh control circuit. Based on this feedback about detected row hammer attacks, the system selectively performs refresh operations only on affected adjacent rows rather than blanket refreshing, thereby maintaining data retention while minimizing disruption to normal memory operations.
Data Source
AI summary
Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address, and a refresh control circuit to perform a RH refresh operation on a memory address array related to the RH address. The RH control circuit includes first latches each to store an old row address used to access the memory and second latches provided correspondingly to the first latches each set to a state indicating whether the old row address stored in one of the first latches is valid. The RH control circuit further including a signal generator configured to assert a sample signal when a new row address to be used to access the memory array matches the old row address stored in any one of the first latches is valid based on a state of one of the second latches.