Row Hammer Detection Circuit Throttling Aggressor Threads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high dynamic random access memory (DRAM) capacity is hindered by wordline electromagnetic coupling (crosstalk) issues, particularly 'row hammering' attacks, which can intentionally induce errors and compromise memory reliability due to high process variation and parasitic capacitances in advanced technology nodes below 22 nm, threatening both current and future DRAM technologies.
Innovation Solution
A detection circuit identifies and throttles aggressor threads performing row hammer attacks by reducing memory access frequency below a predetermined threshold, employing mechanisms such as dynamic frequency and voltage scaling, pipeline stage stalling, and probabilistic filtering to mitigate the impact on adjacent memory rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM capacity is increased by scaling down memory technology and packing more cells in the same die area, then memory capacity increases, but wordline electromagnetic coupling (crosstalk) increases leading to disturbance errors
Solution Approach 1:
The system proactively monitors and detects row hammer attacks before they can cause memory errors. By implementing a detection circuit that counts wordline activations and identifies aggressive access patterns in advance, the system prevents disturbance errors in adjacent wordlines before they occur, thereby maintaining memory reliability while preserving high DRAM capacity
Solution Approach 2:
A detection circuit is introduced as an intermediary component between the memory controller and the memory array. This circuit monitors wordline activation patterns, identifies row hammer attacks, and triggers mitigation actions (such as refreshing victim rows or throttling aggressor threads), thereby protecting the memory system from crosstalk-induced errors without reducing capacity
2Reliability
If row hammer attacks are detected and mitigated by throttling aggressor threads, then memory reliability improves, but system performance may deteriorate
Solution Approach 1:
The system applies throttling locally only to the specific aggressor thread(s) identified as performing row hammer attacks, rather than throttling all threads. The detection circuit identifies the culprit thread by tracking which thread's memory accesses cause excessive wordline activations, and applies mitigation only to that thread, thereby protecting memory reliability while minimizing impact on overall system performance
Solution Approach 2:
The system applies partial throttling to aggressor threads rather than complete blocking. Instead of entirely stopping the aggressor thread, the system reduces its access frequency to below the row hammering threshold, allowing the thread to continue executing at a reduced rate. This partial action is sufficient to prevent memory errors while maintaining better system performance compared to complete blocking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates row hammer attacks by reducing memory access frequency, thereby enhancing memory reliability and preventing data corruption, while minimizing the impact on co-running threads and maintaining system performance.
Implementation Method 1
wordline electromagnetic coupling (crosstalk) considerably increases in technology nodes below the 22 nm process node
Implementation Method 2
dynamic frequency and voltage scaling (DFVS), which can change the rate at which a processor core executing the aggressor thread executes instructions
Implementation Method 3
strong parasitic capacitances among cells of physically adjacent wordlines
Data Source
AI summary
A method includes receiving an indication that a number of activations of a memory structure exceeds a threshold number of activations for a time period, and in response to the indication, throttling instruction execution for a thread issuing the activations.