Row Hammer Detection Logic for DRAM With Integrated Processor
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Solution Overview
Problem
Existing solutions for mitigating the Row Hammer effect in DRAM memory, such as US publication 2014/0006704A1, are not suitable for DRAM with integrated processors and fail to detect Row Hammer conditions in simple scenarios, requiring time-consuming classification processes that cannot be executed within the minimum time between activation commands.
Innovation Solution
A memory device with integrated processors that includes a detection logic system to monitor activation commands from both external and internal processors, dynamically updating tables to identify frequently activated rows and initiate preventive refreshes before they become aggressor rows, thereby delaying periodic refresh requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a detailed classification method is used to detect Row Hammer conditions, then detection accuracy is improved, but the processing time exceeds the minimum time between activation commands
Solution Approach 1:
The patent divides the detection task into segments by maintaining a table with a limited number of entries (e.g., 16 or 32) that represent subsets of rows. Instead of classifying all rows, the system only needs to monitor and update these segmented entries, significantly reducing the computational complexity and time required while maintaining effective Row Hammer detection.
Solution Approach 2:
The patent applies partial action by monitoring only a subset of rows (those represented in the table entries) rather than all rows in the memory bank. This partial monitoring approach is sufficient to detect Row Hammer conditions in practice, as the table entries are updated to reflect the most relevant row activations, achieving effective detection without the excessive time cost of complete classification.
2Measurement precision
If an external memory controller monitors all activation commands, then Row Hammer detection is improved, but it cannot detect activations generated by the internal processor
Solution Approach 1:
The patent implements self-service by enabling the memory device itself (through its internal logic) to monitor and detect Row Hammer conditions caused by internal processor activations. The memory device autonomously tracks activation commands from both external controllers and internal processors, eliminating the need for external monitoring of internal operations and enabling comprehensive detection of all activation sources.
3Reliability
If preventive refreshes are performed for all potentially affected rows, then data retention is improved, but memory performance deteriorates due to excessive refresh operations
Solution Approach 1:
The patent applies local quality by performing preventive refreshes only on specific victim rows that are adjacent to identified aggressor rows, rather than refreshing all rows in the memory bank. The detection logic identifies which rows are at risk based on activation patterns, and refresh operations are localized to those specific rows, maintaining data retention reliability while minimizing the performance impact of refresh operations.
Data Source
AI summary
A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.