Row Hammer Detector Refresh Controller Memory Device
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the gap between cells in dynamic random access memory (DRAM) decreases, interference from adjacent cells becomes a significant factor in data reliability, leading to row hammer disturbance and affected refresh characteristics, making it difficult to restrict access to specific addresses and maintain data integrity.
Innovation Solution
A memory device and method that include a row hammer detector, refresh controller, and overflow flag bit to manage missed rows by generating a refresh row address and performing a refresh operation when the number of accesses meets a predetermined value or when the buffer queue is full, thereby reducing row hammer disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gap between cells is reduced to increase storage density, then the storage capacity is improved, but interference from adjacent cells increases causing row hammer disturbance
Solution Approach 1:
The patent performs preliminary detection of row access counts and identifies rows that are candidates for row hammer disturbance before the disturbance actually occurs. By detecting when a row has been accessed a specific number of times (N times), the system proactively schedules refresh operations for adjacent rows beforehand, preventing data corruption before it happens.
Solution Approach 2:
The patent implements a feedback mechanism where the row hammer detector continuously monitors row access patterns and provides information to the refresh controller. The refresh controller adjusts refresh operations based on this feedback, dynamically responding to actual access patterns rather than using fixed refresh schedules, thereby adapting to changing workload conditions.
2Reliability
If refresh operations are performed frequently to prevent row hammer disturbance, then data reliability is improved, but power consumption and performance overhead increase
Solution Approach 1:
Instead of performing refresh operations on all rows uniformly, the patent applies refresh operations only to specific rows that are identified as candidates for row hammer disturbance. By targeting only the necessary rows (those adjacent to frequently accessed rows) rather than all rows, the system achieves adequate protection with reduced refresh frequency and lower power consumption.
Solution Approach 2:
The patent applies different refresh strategies to different rows based on their access patterns. Rows that are adjacent to frequently accessed rows receive targeted refresh operations, while other rows follow standard refresh schedules. This localized approach ensures data reliability where needed without unnecessarily consuming power on rows that don't require additional protection.
3Measurement precision
If the buffer queue size is increased to store more row addresses, then the accuracy of row hammer detection is improved, but device complexity and area increase
Solution Approach 1:
The patent stores row addresses in the buffer queue only when specific conditions are met (when a row is accessed N times). Rather than storing all row addresses unconditionally, the system selectively stores only those addresses that are relevant for row hammer detection, reducing buffer queue requirements while maintaining detection accuracy for problematic rows.
Solution Approach 2:
The patent extracts and stores only the necessary information (row addresses that meet the access threshold condition) in the buffer queue, rather than storing complete information about all rows. This selective extraction reduces the amount of data that needs to be buffered while still capturing the essential information needed for row hammer detection and prevention.
Data Source
AI summary
A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.