Row Hammer Management Circuit for DRAM Reliability
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face challenges in defending against row hammer attacks, which can lead to data loss due to frequent access of certain memory cell rows, causing adjacent cells to lose stored charges and requiring frequent refresh operations, thereby degrading system performance.
Innovation Solution
A semiconductor memory device with a row hammer management circuit that counts access frequencies, stores these values, and performs internal read-update-write operations to update count data, using a hammer address queue to identify intensively accessed rows and randomize count data to prevent overflow and performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to maintain cell charges in intensively accessed memory cell rows, then data loss is prevented, but system performance degrades due to increased overhead
Solution Approach 1:
The patent performs preliminary identification of intensively accessed memory cell rows by counting access frequencies and storing these counts in count cells. By proactively identifying victim rows before actual data loss occurs, the system can perform targeted refresh operations only when necessary, rather than continuously refreshing all rows. This preliminary detection mechanism prevents unnecessary refresh operations and maintains system performance while ensuring data integrity.
2Reliability
If count data is continuously incremented for intensively accessed rows, then row hammer attack detection is improved, but the hammer address queue overflows and performance degrades
Solution Approach 1:
The patent changes the parameter of count data by performing random updates instead of continuous incrementation. When a memory cell row is identified as intensively accessed, the count data is updated with a random value rather than simply incrementing. This parameter change prevents the count data from monotonically increasing, thereby avoiding hammer address queue overflow while maintaining the ability to detect row hammer attacks through access frequency analysis.
3Reliability
If access frequency counting is performed for all memory cell rows, then row hammer attack detection is enhanced, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing access frequency counting and random update mechanisms only for specific memory cell rows that are intensively accessed, rather than uniformly for all rows. The row hammer management circuit identifies victim rows through access pattern analysis and applies the complex count cell and random update logic only to these localized areas. This selective approach enhances security against row hammer attacks while minimizing the increase in device complexity by avoiding global application of the mechanism.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.