Row Hammer Refresh Verification via Seed Address Monitoring
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Solution Overview
Problem
Integrated circuits face data errors due to row hammer attacks, which affect adjacent addresses, and existing methods lack effective verification for the accuracy of row hammer refresh operations.
Innovation Solution
An address refresh check method that monitors row addresses for data access, sets a seed address based on repetition rates, determines the address type, and compares the expected and actual refresh addresses to verify the accuracy of row hammer refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a row hammer refresh circuit is added to protect victim rows, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism by monitoring actual refresh addresses and comparing them with expected refresh addresses to generate verification results. This feedback loop ensures the row hammer refresh circuit operates correctly without requiring complete redesign of the refresh mechanism, thus improving reliability while limiting complexity growth.
Solution Approach 2:
The patent introduces an intermediary verification mechanism that sits between the row hammer refresh circuit and the memory array. This intermediary layer monitors and validates refresh operations without directly interfering with the core refresh functionality, allowing the system to gain reliability benefits while isolating the complexity of verification logic from the main refresh circuit.
2Measurement precision
If address verification is implemented for row hammer refresh operations, then execution accuracy is improved, but measurement and detection difficulty increases
Solution Approach 1:
The patent creates a simplified copy or model of the expected refresh address generation process. By implementing an address generation unit that produces expected addresses according to the same decoding policy, the system can verify actual refresh operations without requiring complex analysis of memory hardware behavior, thus improving measurement precision while reducing verification complexity.
Solution Approach 2:
The patent changes the verification approach from monitoring physical memory states to comparing address parameters. By focusing verification on address generation logic and address matching rather than direct memory content verification, the system achieves high execution accuracy through parameter comparison, which is computationally simpler than full memory state detection.
3Reliability
If seed address monitoring and address type determination are implemented, then refresh operation verification is improved, but device complexity increases
Solution Approach 1:
The patent designs the address detection unit and address generation unit to serve multiple functions: they not only generate expected refresh addresses for verification but also identify seed addresses and determine address types. This multi-functionality reduces the need for separate dedicated circuits for each monitoring task, thereby improving verification reliability while limiting the growth of overall device complexity.
Data Source
AI summary
An address refresh check method includes: setting a row address with a highest repetition rate or with a quantity of repetition times exceeding a predetermined threshold as a seed address, and determining an address type; if the address type is a random address, obtaining an expected refresh address; performing a row hammer refresh operation to obtain an actual refresh address; and comparing the expected refresh address with the actual refresh address to obtain a check result.