Row Hammer Tracking Device Using SRAM and Pipeline Read
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Solution Overview
Problem
Existing memory systems face challenges in efficiently detecting row-hammer addresses due to the increasing density of memory chips, which leads to a higher likelihood of row hammering and performance degradation.
Innovation Solution
A memory controller with a row-hammer tracking device that uses static random access memory (SRAM) instead of content addressable memory (CAM) to store candidate addresses and access counting values, allowing for efficient detection of row-hammer addresses through a pipeline read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If content addressable memory (CAM) is used to store candidate addresses and access counting values, then detection precision of row-hammer addresses is improved, but device area increases significantly
Solution Approach 1:
The patent uses SRAM to store copies of candidate addresses and access counting values instead of using CAM. The SRAM-based implementation maintains the necessary tracking functionality while occupying significantly less area than CAM, thus resolving the contradiction between detection precision and device area.
Solution Approach 2:
The patent changes the storage medium parameter from CAM to SRAM. This parameter change allows the system to maintain address tracking capability while reducing the area occupation, as SRAM has a much smaller footprint per bit compared to CAM.
2Speed
If traditional non-pipeline read operation is used from storage devices, then device complexity is reduced, but detection speed of row-hammer addresses decreases
Solution Approach 1:
The patent implements a pipeline read operation that dynamically processes multiple storage devices in parallel stages. The search controllers operate in a pipelined manner where each stage processes different storage devices simultaneously, increasing detection speed while managing complexity through structured parallelism.
Solution Approach 2:
The patent divides the read operation into multiple pipeline stages, with each search controller handling a specific stage. This segmentation allows simultaneous processing of multiple storage devices across different pipeline stages, thereby increasing detection speed without proportionally increasing overall device complexity.
3Productivity
If memory chip density is increased to improve productivity, then output per unit time is improved, but row hammering likelihood increases causing performance degradation
Solution Approach 1:
The patent performs preliminary tracking of access counts for each candidate address before row hammering can cause damage. By continuously monitoring and counting accesses in advance, the system can identify potentially vulnerable addresses and apply protective refresh operations before data corruption occurs, thus maintaining reliability despite increased density.
Solution Approach 2:
The patent implements a feedback mechanism where access counting values are continuously updated and compared against thresholds. When a candidate address reaches a predetermined access count threshold, the system triggers a protective refresh operation on the corresponding memory row, preventing row hammering damage and maintaining performance stability in high-density memory systems.
Data Source
AI summary
A memory controller includes a command/address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command/address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.