Memory Row Hammer Detection With Targeted Victim Row Refresh
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Solution Overview
Problem
Semiconductor memory devices face challenges in managing row hammer effects, where intensive access to certain memory cell rows leads to charge leakage in adjacent cells, requiring frequent refresh operations that increase power consumption and overhead, especially as memory capacity increases.
Innovation Solution
A semiconductor memory device and system that includes a row hammer management circuit to count access frequencies of memory cell rows, identify intensely accessed rows, and perform internal read-update-write operations to update count data, while a refresh control circuit performs hammer refresh operations on adjacent victim cells, reducing power consumption and overhead through time multiplexing of user and count data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent charge leakage in victim memory cell rows, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary detection of row hammer events by counting access frequencies to victim memory cell rows before data loss occurs. The row hammer management circuit identifies intensely accessed rows and proactively triggers refresh operations, preventing charge leakage before it compromises data reliability, thereby reducing the need for continuous frequent refreshing and lowering overall power consumption.
Solution Approach 2:
The patent implements a feedback mechanism where the row hammer management circuit continuously monitors access frequencies to memory cell rows, compares them against thresholds, and dynamically adjusts refresh operations based on detected row hammer events. This feedback-driven approach ensures refresh operations are performed only when necessary, optimizing the balance between data reliability and power consumption.
2Reliability
If comprehensive row hammer management is implemented for all memory cell rows, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory management function by separating row hammer detection and management from the main memory control logic. A dedicated row hammer management circuit is introduced that independently counts access frequencies, identifies victim rows, and triggers refresh operations. This segmentation allows comprehensive row hammer management across all memory cell rows while isolating the complexity to a specialized module, minimizing impact on the overall device architecture.
Solution Approach 2:
The row hammer management circuit operates autonomously to detect and manage row hammer events without requiring external intervention. It self-monitors access frequencies, automatically identifies victim memory cell rows, and triggers refresh operations independently, reducing the management overhead and simplifying the overall system control while maintaining comprehensive protection.
3Reliability
If access frequency counting and refresh operations are performed for all memory cell rows, then row hammer management effectiveness is improved, but overhead increases
Solution Approach 1:
The patent applies partial action by focusing row hammer management resources only on victim memory cell rows that are intensely accessed and identified as susceptible to row hammer events. Rather than uniformly managing all memory cell rows, the system selectively applies refresh operations to affected rows based on access frequency thresholds, reducing overhead while maintaining effective row hammer management where needed.
Solution Approach 2:
The system performs preliminary identification of victim rows through access frequency counting before row hammer effects manifest. By detecting intensely accessed rows in advance and proactively triggering refresh operations, the system prevents data loss without requiring continuous monitoring and refreshing of all memory cell rows, thereby reducing time overhead while maintaining effective row hammer management.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.