Row Hammering Tracking in Semiconductor Memory Systems
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Solution Overview
Problem
As semiconductor devices experience increased integration, the row hammering phenomenon leads to interference between adjacent word lines, causing data loss due to changes in charge storage in memory cell capacitors, which existing technologies fail to effectively mitigate.
Innovation Solution
A semiconductor system with a controller that performs row hammering tracking operations, including generating commands and addresses for tracking write and read operations, and a row hammering storage circuit to count active bank numbers, allowing for precharge operations based on these commands, thereby reducing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased, then productivity and device density are improved, but the row hammering phenomenon occurs causing data loss due to interference between adjacent word lines
Solution Approach 1:
The patent performs a tracking read operation before the actual write operation to detect and count the number of active banks that will be affected by the subsequent write. This preliminary action allows the system to identify potential row hammering victims in advance and adjust the refresh timing accordingly, preventing data loss before it occurs
Solution Approach 2:
The patent implements a feedback mechanism where the controller counts the number of active banks through tracking read operations, and uses this count information to dynamically adjust the refresh operation timing. The refresh timing is determined based on the counted active bank number, creating a closed-loop system that adapts to actual memory state and prevents row hammering-induced data loss
2Reliability
If refresh operations are performed to prevent data loss, then reliability is improved, but operation time and system complexity increase
Solution Approach 1:
The patent changes the timing parameter of refresh operations dynamically based on the number of active banks counted during tracking read operations. Instead of performing refresh operations at fixed intervals or for all banks uniformly, the system adjusts refresh timing parameters according to the actual number of affected banks, reducing unnecessary refresh operations and optimizing operation time
Solution Approach 2:
The patent performs refresh operations only on the specific number of banks that are actually affected by row hammering, as determined by the tracking read operation count. Rather than refreshing all banks or using a conservative fixed number, the system applies refresh actions precisely to the partial set of affected banks, minimizing wasted operation time while ensuring adequate protection
Data Source
AI summary
A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.