Hardware-Accelerated Row Lock for Write Back Volume Caching

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Solution Overview

Problem

Traditional caching algorithms in MegaRAID systems require region locks to prevent data inconsistency, leading to reduced performance in high I/O operations, especially in RAID 5/6 volumes, where parallel threads performing flush operations need to be serialized.

Innovation Solution

The proposed solution involves a hardware-managed flow that avoids region locks by using granular locks, allowing concurrent processing of read and write commands without locks on optimal volumes, and employs implicit write coalescing and outstanding read counts to manage flush operations, ensuring no locks are needed for full cache hits and avoiding flushes on degraded volumes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If region locks are used to prevent data inconsistency in traditional caching algorithms, then data consistency is ensured, but performance is reduced due to serialization of parallel threads

Engineering Contradiction:
Improvedata consistencyVSAvoidIOPS
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the caching system into multiple independent cache lines, each with its own lock. Instead of using a single region lock that serializes all operations, the system segments the cache into discrete units (cache lines) that can be locked independently. This allows multiple threads to operate on different cache lines simultaneously, maintaining data consistency within each cache line while enabling parallel execution across the cache, thus resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If region locks are used to serialize flush operations, then data consistency is maintained, but latency increases due to reduced concurrency

Engineering Contradiction:
Improvedata consistencyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the cache into multiple cache lines, each capable of being flushed independently with its own lock. This segmentation allows flush operations to proceed in parallel on different cache lines rather than serializing all flush operations through a single region lock. The fine-grained locking at the cache line level maintains data consistency while reducing latency by enabling concurrent flush operations across multiple cache lines.

Inventive Principle:
Principle #1Segmentation

3Reliability

If region locks are used to prevent overlapping reads and writes, then data consistency is ensured, but throughput decreases due to artificial bottlenecks

Engineering Contradiction:
Improvedata consistencyVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements fine-grained locking at the cache line level rather than using coarse-grained region locks. Each cache line has its own lock, allowing multiple threads to simultaneously access different cache lines for reads and writes. This segmentation eliminates the artificial bottleneck created by region locks, as threads can now operate in parallel on different cache lines while maintaining data consistency through the finer-grained locking mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies locking only where necessary - at the specific cache line level rather than across entire regions. This local quality approach ensures that data consistency is maintained at the precise location where conflicts can occur (individual cache lines) while allowing other parts of the cache to remain unlocked and accessible to multiple threads simultaneously, thereby maximizing throughput without sacrificing reliability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10649906B2Method and system for hardware accelerated row lock for a write back volume
Publication Date: 2020.05.12 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US10649906B2 patent drawing
  • US10649906B2 patent drawing
  • US10649906B2 patent drawing

AI summary

A system and method for efficient cache flushing are provided. The disclosed method includes maintaining a data structure in connection with a plurality of blocks used for data caching, the data structure including a row lock wait list section. The method further includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against the data structure, and based on the results of the hash search, locking at least one row in a data cache thereby preventing read and write operations from being performed on the at least one row until the at least one row is unlocked.