Row Mask Addressing for Partial Memory Access
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Solution Overview
Problem
Power consumption in electronic devices, particularly in complex memory systems, leads to resource depletion and performance degradation due to the need to access all memory cells in a row, resulting in inefficiencies and increased operational costs.
Innovation Solution
A method and apparatus that generate a row address mask to selectively access only a portion of memory cells in a memory array, using additional bits to block access signals and reduce power consumption by turning on only necessary local access-lines, thereby allowing for partial selection of rows during read, write, and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cells in a row are accessed using conventional memory technology, then complete row access is achieved, but power consumption increases significantly
Solution Approach 1:
The patent segments the row access operation into two independent parts: (1) global row selection via word-line activation, and (2) local column selection via bit-line activation. The row mask register divides the row into multiple segments, allowing selective activation of only the required column segments. This segmentation enables partial row access, reducing the number of active bit-lines and thereby reducing power consumption while maintaining access to the required memory cells.
Solution Approach 2:
The patent implements partial action by allowing access to only the necessary portion of the row rather than the entire row. The row mask register enables selective activation of specific column segments, so that only the required memory cells are accessed. This partial access approach reduces power consumption by avoiding activation of unnecessary bit-lines and sense amplifiers, while still providing complete access to the required data.
2Use of energy by moving object
If additional row address bits are used to selectively access portions of a row, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a row mask register as an intermediary component between the address decoder and the memory array. This register receives the row address and additional row mask bits, then generates control signals that selectively activate bit-line segments. The row mask register acts as a mediator that translates the additional address bits into precise control signals, enabling partial row access without requiring complex modifications to the core memory architecture or decoding logic.
Solution Approach 2:
The patent adds a new dimension to the addressing scheme by introducing row mask bits that operate independently of the conventional row and column addresses. These additional bits provide a new degree of freedom for controlling memory access, allowing selective activation of column segments within a selected row. This dimensional extension enables fine-grained power management without fundamentally altering the existing address decoding mechanism.
3Use of energy by moving object
If local access-lines are selectively activated, then power consumption decreases, but access time may increase due to additional control logic
Solution Approach 1:
The patent implements preliminary action by pre-charging and pre-enabling the required bit-line segments before the actual memory access operation. The row mask register is configured in advance to identify which column segments will be accessed, and the corresponding bit-lines are prepared accordingly. This preliminary preparation ensures that when the access operation commences, the required bit-lines are already in the correct state, minimizing access time overhead while still achieving power savings through selective activation.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that the selective bit-line activation does not interrupt the normal memory access flow. The row mask control logic operates in parallel with the address decoding process, and the selected bit-lines remain active throughout the entire access operation. This continuous operation ensures that the reduced scope of activation does not create timing gaps or delays, maintaining efficient access speeds while reducing power consumption.
Data Source
AI summary
Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.