Row-Oriented SRAM Write Assist Circuit for Low Power
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Solution Overview
Problem
As integrated circuit lithography advances, SRAM cells face challenges in maintaining robust operation across varying process, voltage, and temperature conditions due to increased variability in transistor performance, necessitating the use of read and write assist circuits, which incur costs in terms of area and power consumption.
Innovation Solution
A row-oriented write assist circuit that temporarily reduces the internal supply voltage to selected rows of SRAM bit cells, using a PFET transistor and an NFET assist transistor to lower power consumption and maintain data reliability, unlike traditional column-oriented approaches that discharge power supply voltage for entire columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional column-oriented write assist circuits are used to reduce power consumption, then power dissipation is reduced, but data loss occurs in non-accessed rows and write assist capability is weakened
Solution Approach 1:
The patent segments the write assist function from column-oriented to row-oriented implementation. Instead of discharging the entire column power supply voltage, the invention applies write assist only to the specific row being written by temporarily discharging the row power supply voltage (VDD_ROW) through a write assist transistor. This segmentation allows power reduction without affecting data retention in non-accessed rows, as only the targeted row experiences voltage discharge during write operations.
2Area of moving object
If SRAM cell size is reduced to increase integration density, then manufacturing capacity increases, but transistor performance variability increases making robust operation difficult
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the power supply voltage (VDD_ROW) to a lower level during write operations. This temporary voltage reduction weakens the pull-up transistors in the selected row, facilitating easier data writing into SRAM cells. The parameter change is localized to only the row being written, maintaining robust operation in non-accessed rows while enabling reliable writes in scaled-down cells with higher variability.
3Reliability
If read and write assist circuits are added to maintain robust operation in scaled SRAM, then operation reliability improves, but area and power consumption increase
Solution Approach 1:
The patent implements periodic action by temporarily discharging the row power supply voltage (VDD_ROW) only during the brief write operation window. The write assist transistor is activated momentarily to reduce VDD_ROW, providing assist exactly when needed for the write operation, then deactivating to restore normal voltage levels. This periodic, on-demand assist minimizes power consumption compared to continuous assist mechanisms, while maintaining robust operation during critical write moments.
Data Source
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AI summary
Aspects of the present disclosure generally relate to static random access memory (SRAM), and more specifically, to a low-power, row-oriented memory write assist circuit. The SRAM may generally comprise an array of bit cells arranged in rows and columns, wherein each bit cell in a row is selected for writing via a corresponding wordline for that row and wherein each bit cell in a column is coupled to a corresponding pair of bitlines for supplying complementary data values, and at least one row-oriented write assist circuit configured to temporarily reduce, to a desired voltage level, a voltage on an internal voltage line used to supply power to the bit cells of a row selected for writing.