Row-Orthogonal QC-LDPC Encoding for Low-Latency Error Correction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current wireless communication systems, particularly in LTE, face challenges with high error rates and complexity, which are exacerbated by the limited performance of turbo codes beyond a certain signal-to-noise ratio, and require a coding method that balances low error rates with low complexity to meet the demands of 5G communication standards like ultra-reliable and low-latency communications.

Innovation Solution

The implementation of a quasi-cyclic low-density parity-check (LDPC) code method using a multi-edge LDPC code matrix, specifically formed by concatenating a high rate code matrix and a single parity check code matrix with a quasi-row-orthogonal and pure row-orthogonal structure, to encode signals efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a code with low error rate is used to improve reliability, then the error rate decreases, but the complexity increases

Engineering Contradiction:
Improveerror rateVSAvoidcoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC code is segmented into multiple blocks or groups, allowing the encoding process to be divided into smaller, more manageable operations. This segmentation reduces the overall computational complexity while maintaining the low error rate characteristics of LDPC codes through structured parity-check matrices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs parameter optimization by adjusting the LDPC code rate, block length, and parity-check matrix structure to achieve the desired error rate performance. By carefully selecting code parameters, the system attains low error rates without requiring excessive computational complexity, balancing reliability and implementation feasibility.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a code with high complexity is used to reduce error rate, then the error rate decreases, but the overhead and latency increase

Engineering Contradiction:
Improveerror rateVSAvoidtransmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By segmenting the LDPC encoding process into smaller operations through structured parity-check matrices, the patent reduces the time required for encoding and transmission. This segmentation allows for more efficient processing with lower latency while maintaining error correction capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality optimization by using structured parity-check matrices with specific patterns (e.g., circulant, quasi-cyclic structures) in different parts of the code. This localized structural optimization enables faster decoding algorithms to be applied, reducing overall transmission latency while maintaining low error rates.

Inventive Principle:
Principle #3Local quality

3Reliability

If a code with high complexity is used to reduce error rate, then the error rate decreases, but the overhead of base station and user equipment increases

Engineering Contradiction:
Improveerror rateVSAvoidbase station and UE overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs universal LDPC code structures with standardized parity-check matrices that can be implemented efficiently in both base stations and user equipment. This multi-functionality allows the same encoding and decoding algorithms to be used across different devices, reducing implementation overhead and simplifying system deployment while achieving low error rates.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11082060B2LPDC code transmission method using row-orthogonal structure and apparatus therefor
Publication Date: 2021.08.03 LG ELECTRONICS INC
  • US11082060B2 patent drawing
  • US11082060B2 patent drawing
  • US11082060B2 patent drawing

AI summary

A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.