Row Address Repeater Group Control for Lower-Power Memory Banks
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in managing power consumption efficiently during bank operations, particularly in volatile memory devices like DRAM, due to leakage currents and the need to maintain data retention without continuous power supply.
Innovation Solution
A memory device is designed with grouped memory banks and corresponding row address repeaters, where a control logic selectively activates only the necessary repeater groups based on the activation status of bank groups, and applies data bus inversion technology to reduce power consumption by optimizing row address signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all row address repeaters are continuously activated to ensure data retention in volatile memory devices, then data integrity is maintained, but power consumption increases due to leakage currents
Solution Approach 1:
The memory device divides row address repeaters into multiple independent groups (first repeater group, second repeater group, third repeater group) corresponding to different bank groups. Each repeater group can be independently activated or deactivated based on which bank group is currently active, preventing unnecessary power consumption in inactive repeater groups while maintaining data integrity in active groups.
Solution Approach 2:
The control logic dynamically adjusts the activation state of row address repeater groups based on real-time bank group activation status. When a bank group is deactivated, its corresponding repeater group is also deactivated to reduce power consumption. This dynamic adaptation allows the system to optimize power usage without compromising data retention in actively used memory regions.
2Use of energy by moving object
If row address repeaters are deactivated to reduce power consumption, then energy usage decreases, but signal transfer capability is lost
Solution Approach 1:
By segmenting row address repeaters into multiple groups tied to specific bank groups, the system ensures that only the repeater group corresponding to the active bank group remains activated. This segmentation maintains signal transfer capability for currently accessed memory banks while deactivating other repeater groups to reduce power consumption.
Solution Approach 2:
The control logic acts as an intermediary that monitors bank group activation status and accordingly controls the activation of corresponding repeater groups. This intermediary function ensures that signal transfer capability is maintained precisely when needed (when bank groups are active) while eliminating unnecessary signal transfer operations that would consume power.
3Use of energy by moving object
If data bus inversion is applied to all repeater groups, then power consumption is reduced through optimized signal transfer, but device complexity increases
Solution Approach 1:
Data bus inversion is applied selectively to individual repeater groups based on their specific operational context and distance from I/O pads, rather than uniformly to all repeater groups. This localized application of inversion optimizes power consumption in each region while minimizing the overall control logic complexity required to manage the inversion states.
Data Source
AI summary
Disclosed is a memory device, which may include memory banks including a plurality of memory cells, row address repeaters that transfer a row address to the memory banks, and control logic that controls data input/output of the memory banks. The memory banks may be grouped into a plurality of bank groups, and the row address repeaters may be grouped into a plurality of repeater groups respectively corresponding to the plurality of bank groups. The control logic may control the row address repeaters according to activation status of the plurality of bank groups.