Stacked Image Sensor Row-Scan Layout to Eliminate Empty Chip Area

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Solution Overview

Problem

In large-sized image capturing devices with a stacked chip structure, the circuit chip often experiences wasteful empty regions due to the increased size of the scanning section, leading to inefficient area utilization.

Innovation Solution

The image capturing device is designed with a stacked chip structure where the scanning section is arranged along pixel rows on the second semiconductor chip, optimizing the layout to prevent wasteful empty regions, and the signal processing section includes analog-to-digital conversion units proportional to the pixel columns, with flexible wiring configurations to enhance area efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the scanning section is arranged along pixel columns in a large-sized image capturing device, then the scanning function is achieved, but wasteful empty regions are caused in the circuit chip

Engineering Contradiction:

Improvescanning functionVSAvoidarea utilization of circuit chip

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies inversion by changing the arrangement direction of the scanning section from along pixel columns to along pixel rows. This reverse approach to the conventional layout allows the scanning section to be positioned along the long side of the pixel array, enabling the circuit chip to be sized to match the pixel chip dimensions without creating wasteful empty regions, thus resolving the area utilization problem while maintaining scanning functionality

Inventive Principle:

Principle #13The other way round (Inversion)

2Area of moving object

If the pixel array section area is increased, then the image capturing capability is improved, but the scanning section size increases causing empty regions in the circuit chip

Engineering Contradiction:

Improvepixel array section areaVSAvoidcircuit chip area efficiency

Core Design Contradiction:

Area of moving objectVSArea of stationary object

Solution Approach 1:

By inverting the conventional arrangement approach and positioning the scanning section along pixel rows instead of columns, the patent enables the circuit chip to scale with the pixel array section area without proportionally increasing empty regions. This allows larger pixel arrays to be accommodated while maintaining high area efficiency on the circuit chip

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent utilizes dimensional optimization by arranging the scanning section along the row direction (horizontal dimension) rather than the column direction (vertical dimension). This dimensional change allows better spatial utilization on the circuit chip, enabling the circuit chip to match the pixel chip size without creating excessive empty spaces even as the pixel array area increases

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12120449B2Image capturing device and electronic apparatus with stacked chip structure

Publication Date: 2024.10.15 SONY SEMICON SOLUTIONS CORP

AI summary

An image capturing device of the present disclosure has a stacked chip structure in which at least two semiconductor chips including a first semiconductor chip and a second semiconductor chip are stacked. Pixels each including a light receiving portion are arranged on the first semiconductor chip, and a scanning section that selectively scans the pixel and a signal processing section that processes an analog signal output from the pixel are arranged on the second semiconductor chip. Further, the scanning section is arranged along pixel rows of the pixel arrangement in the matrix form.