Rowhammer Mitigation via Varying Wordlines in DRAM
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Solution Overview
Problem
Rowhammer attacks exploit hardware vulnerabilities in DRAM devices by inducing bit flips in adjacent memory rows, potentially leading to security breaches by altering permissions or program behavior.
Innovation Solution
The solution involves optimizing row-address decoders by varying wordlines across memory access tiles (MATs) to limit the impact of Rowhammer attacks, ensuring that bit flips are confined to a limited number of bits within a single MAT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional row-address decoders are used in DRAM devices, then memory access speed and bandwidth are maintained, but the device becomes vulnerable to Rowhammer attacks that can induce bit flips in adjacent memory rows
Solution Approach 1:
The memory array is divided into multiple independently decodable banks, where each bank has its own row-address decoder. This segmentation isolates Rowhammer attacks to specific banks, preventing attacks from affecting the entire memory array. The patent implements this by creating multiple banks with separate decoder circuits, so that an attack on one bank does not propagate to other banks.
Solution Approach 2:
Different row-address decoding schemes are applied to different banks based on their specific security requirements and attack vectors. Each bank can use customized decoding patterns, refresh strategies, or error correction codes tailored to its local security needs, rather than applying a uniform approach across the entire memory device.
2Object-affected harmful factors
If row-address decoders are optimized to vary wordlines across memory access tiles, then the impact of Rowhammer attacks is limited to fewer bits, but the decoder complexity increases
Solution Approach 1:
The row-address decoding uses asymmetric patterns where adjacent row addresses are intentionally mapped to non-adjacent physical wordlines in a systematic but irregular pattern. This asymmetric mapping ensures that Rowhammer attacks targeting adjacent physical rows do not consistently affect the same logical addresses, thereby reducing the number of bits that can be flipped. The patent implements this through customized decoding tables that break the direct correlation between adjacent address values and adjacent physical locations.
Solution Approach 2:
The patent introduces an additional dimension to the addressing scheme by using multi-stage decoding where row addresses are first decoded to bank identifiers and then to wordline selections within each bank. This dimensional transformation allows the system to spread out adjacent addresses across different spatial dimensions (banks and wordlines), reducing the concentration of vulnerable adjacent bits that Rowhammer attacks exploit.
3Reliability
If multiple independent banks with separate decoders are created, then Rowhammer attack impact is isolated, but the overall device area and manufacturing complexity increase
Solution Approach 1:
The row-address decoder circuit is designed as a universal, reusable module that can be instantiated multiple times across different banks. Each decoder instance performs the same function but operates independently on its assigned bank. This modular universal design allows the system to achieve fault isolation through replication while minimizing the area overhead compared to designing completely separate custom decoders for each bank.
Solution Approach 2:
The patent implements a hierarchical bank structure where smaller memory access tiles are nested within larger banks, and multiple banks are nested within the overall memory array. This nested organization allows Rowhammer attacks to be contained at the tile level, with intermediate containment at the bank level, providing progressive isolation that reduces the required decoder complexity and area compared to complete independence at all levels.
Data Source
AI summary
Technologies for Rowhammer mitigation in a memory die are described. A dynamic random-access memory (DRAM) device includes a plurality of memory array tiles (MATs), each MAT comprising multiple rows and columns of memory cells. Each MAT of the plurality of MATs having a plurality of main wordlines (MWLs) and a plurality of sub-wordlines (SWLs). Each row in the respective MAT corresponds to a SWL and each column in the respective MAT corresponds to a bitline (BL). For an activate command received by the DRAM device, a set of intermediate MWLs is enabled and different SWLs are activated from each MWL of the set of intermediate MWLs such that the different SWLs in each MAT are varied. The varying SWLs across MATs can serve as a Rowhammer mitigation mechanism. The Rowhammer mitigation mechanism can be used in connection with an error detection mechanism to detect failures caused by a Rowhammer attack.