Contactor Pin Block Depopulation for RPC Semiconductor Testing

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Solution Overview

Problem

Testing of packaged semiconductor devices with reduced pin count (RPC) often results in erroneous test results due to misconfigured contactor pin blocks, leading to subtle yield loss and delayed detection of issues, which can cause revenue loss and affect product qualification.

Innovation Solution

The implementation of error-proof methodologies for configuring RPC contactor pin blocks, including the use of dummy plugs in voided sockets, a retainer plate to cover depopulated sockets, and a glass mask with marks to ensure accurate pin placement, prevents accidental re-insertions and ensures correct testing of only necessary pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If pins are manually depopulated from contactor sockets for RPC devices, then testing cost is reduced, but erroneous test results occur due to misconfiguration

Engineering Contradiction:

Improvetesting costVSAvoidtest result accuracy

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-configuring the contactor pin block with pins in sockets corresponding to leads that require testing, before the actual testing process begins. This pre-configuration ensures that only necessary pins are populated, preventing misconfiguration errors while maintaining cost efficiency for RPC devices.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary approach by introducing a mapping mechanism between device leads and contactor pins. This intermediary system ensures correct correspondence between leads and pins, preventing erroneous test results while maintaining the reduced pin count configuration for cost efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If all leads are tested in RPC devices, then comprehensive testing is achieved, but testing time increases

Engineering Contradiction:

Improvetesting completenessVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies the extraction principle by removing pins from sockets that correspond to leads not requiring testing in RPC devices. This selective removal reduces the number of pins that need to be tested, thereby decreasing testing time while maintaining comprehensive testing for all necessary leads through the configured pin-lead mapping.

Inventive Principle:

Principle #2Taking out (Extraction)

3Device complexity

If pin placement is not verified, then setup process is simplified, but yield loss occurs due to misconfiguration

Engineering Contradiction:

Improvesetup process complexityVSAvoidyield

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements feedback by verifying pin placement correspondence with device leads through a mapping system. This feedback mechanism confirms that pins are correctly positioned in sockets corresponding to leads requiring testing, preventing yield loss from misconfiguration while maintaining manageable setup process complexity.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11493535B2Systems and methods for depopulating pins from contactor test sockets for packaged semiconductor devices

Publication Date: 2022.11.08 TEXAS INSTRUMENTS INC

AI summary

A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.