RQL Circuit Synthesis Using Flip-Flop Placeholders and Clock Phasing

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Solution Overview

Problem

Current CMOS synthesizers struggle to efficiently design Reciprocal Quantum Logic (RQL) circuits, particularly due to the inability to replicate edge-triggered flip-flop devices, which are essential for synchronous design methodologies, as they require sequential FF elements not available in typical RQL component libraries.

Innovation Solution

A method involving a synthesis tool that generates RQL netlist circuits with flip-flop device placeholders, replaces them with sequentially controlled flip-flop devices, and separates the circuit system into subsystems associated with different clock phases, allowing for the simulation and optimization of RQL circuits by emulating CMOS flip-flop functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If CMOS synthesizers use standard component libraries for circuit synthesis, then the synthesis process is efficient and automated, but the ability to design RQL circuits with edge-triggered flip-flop functionality is lost

Engineering Contradiction:

Improveautomation of circuit synthesisVSAvoidability to design RQL circuits with flip-flop functionality

Core Design Contradiction:

Extent of automationVSAdaptability or versatility

Solution Approach 1:

The patent creates a placeholder component that copies the behavioral interface of a CMOS flip-flop in the RQL netlist, allowing the synthesis tool to generate RQL circuitry that emulates flip-flop functionality without requiring actual flip-flop devices in the component library. This enables automated synthesis while maintaining RQL-specific design capabilities.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The placeholder component acts as an intermediary between the CMOS synthesis tool and the RQL implementation. It allows the synthesis tool to operate with familiar flip-flop abstractions while the backend translates these into RQL-compatible circuitry using Josephson transmission lines and other RQL components.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If RQL circuits use Josephson transmission lines as sequential devices, then the circuits can operate at higher speeds, but the strict combinatorial and sequential classifications used in CMOS synthesis no longer apply

Engineering Contradiction:

Improveoperating speed of RQL circuitsVSAvoidcomplexity of circuit synthesis methodology

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the circuit synthesis process into distinct phases: behavioral modeling phase (using placeholder components with flip-flop interfaces), synthesis phase (generating RQL netlist), and implementation phase (mapping to physical RQL components). This segmentation allows each phase to handle the appropriate level of abstraction and complexity independently.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic phase signaling into the RQL circuit design, where clock signals are distributed across multiple phases to different circuit subsystems. This dynamic timing control enables high-speed operation while the synthesis tool manages the complexity of phase coordination through systematic clock tree generation and synchronization.

Inventive Principle:

Principle #15Dynamics

3Ease of manufacture

If RQL circuits are designed without flip-flop placeholders, then the component library remains simple, but the synthesis tool cannot generate clock-triggered sequential behavior

Engineering Contradiction:

Improvesimplicity of component libraryVSAvoidability to implement synchronous design methodology

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The placeholder component is a temporary, disposable element used only during the synthesis process. It serves its purpose of enabling flip-flop behavioral modeling, is removed from the final RQL netlist, and replaced with actual RQL sequential circuitry. This allows the component library to remain simple while temporarily providing flip-flop functionality when needed.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The placeholder component is inserted preliminary to the actual RQL circuit generation. It establishes the flip-flop behavioral framework early in the synthesis process, allowing the tool to systematically generate clock-triggered sequential logic, which is then translated into RQL-specific implementations before the placeholder is removed.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10061883B2Reciprocal quantum logic (RQL) circuit synthesis

Publication Date: 2018.08.28 NORTHROP GRUMMAN SYSTEMS CORP

AI summary

One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.