RQL NDRO Circuits With Body-Tail Topology for Simultaneous Read-Write

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Solution Overview

Problem

Conventional superconducting non-destructive readout circuits in quantum and classical digital systems face challenges in reducing device count, improving functionality, and allowing simultaneous writing and reading operations, while minimizing the use of large transformers.

Innovation Solution

The development of reciprocal quantum logic (RQL) non-destructive readout (NDRO) gates and demultiplexer circuits utilizing a body-tail topology with single flux quantum (SFQ) logical inputs and Josephson junctions, enabling non-destructive readout of stored logical states without affecting the stored information, and allowing for simultaneous writing and reading operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional superconducting non-destructive readout circuits are used, then readout functionality is achieved, but device count (Josephson junctions and inductors) is high

Engineering Contradiction:
Improvedevice countVSAvoidcircuit complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The readout circuit is divided into separate functional blocks: a readout circuit block with first and second Josephson junctions for non-destructive readout, and a write circuit block with third and fourth Josephson junctions for write operations. This segmentation allows independent optimization of each block, reducing overall device count while maintaining functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The same Josephson junctions and circuit elements are used for multiple functions. The readout circuit block can perform both non-destructive readout and participate in write operations, while the body circuit serves as both storage and readout target. This multi-functionality reduces the total number of required Josephson junctions and inductors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If conventional readout circuits are used, then readout is achieved, but simultaneous write and read operations are not possible

Engineering Contradiction:
Improveoperational throughputVSAvoidcircuit architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The circuit is segmented into distinct readout and write circuit blocks that can operate independently and simultaneously. The readout circuit block with its dedicated Josephson junctions can perform readout while the write circuit block performs write operations, enabling simultaneous operations without interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The body circuit acts as an intermediary between the readout and write circuit blocks. It receives write signals from the write circuit block and provides the state for non-destructive readout by the readout circuit block, enabling coordinated simultaneous operations while maintaining data integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If traditional NDRO circuits are used, then non-destructive readout is achieved, but memory and logic cell density is low

Engineering Contradiction:
Improvecell densityVSAvoidcircuit structure
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The readout and write circuit blocks are merged into a single integrated circuit structure sharing common elements like the body circuit and ground connections. This merging reduces the total area required per functional unit, increasing cell density while maintaining the non-destructive readout capability through the specialized Josephson junction configuration.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The RQL NDRO circuits reduce the number of Josephson junctions and inductors, increase memory and logic cell density, and enable efficient, compact memory arrays with improved functionality, including simultaneous read and write capabilities, thus enhancing computing and memory operations.

Implementation Method 1

Each tail circuit in the NDRO gate includes a tail input inductor connected between an NDRO read-enable input port and the body circuit and configured to receive an SFQ pulse NDRO read-enable signal

Methodology Applied
Scientific EffectSingle flux quantum (SFQ): Josephson Effect

Implementation Method 2

a tail Josephson junction connected between the body circuit and a circuit ground

Methodology Applied
Scientific EffectJosephson junction: Josephson Effect

Implementation Method 3

a tail output inductor connected between the body circuit and an NDRO output port and configured to transmit an SFQ pulse NDRO output signal based on the stored logical state

Methodology Applied
Scientific EffectSingle flux quantum (SFQ): Josephson Effect

Data Source

PatentUS11159168B2Superconducting non-destructive readout circuits
Publication Date: 2021.10.26 NORTHROP GRUMMAN SYSTEMS CORP
  • US11159168B2 patent drawing
  • US11159168B2 patent drawing
  • US11159168B2 patent drawing

AI summary

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.