RQL Serial Receiver Oversampling for Cryogenic Clock Recovery
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Solution Overview
Problem
Superconducting digital technology lacks a suitable method for high-speed serial data transfer, as phase-locked loops (PLLs) do not exist in reciprocal quantum logic (RQL) systems, and CMOS data transfer techniques are unsuitable for cold environments, hindering efficient data capture and clock recovery.
Innovation Solution
A reciprocal quantum logic (RQL) receiver system that oversamples a serial input data stream using a quadrature clock signal, detecting transitions and capturing digital values through a sampling controller with an edge detector and integrator system, effectively emulating PLL functionality without requiring phase-locked loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CMOS data transfer techniques are used in superconducting environments, then high-speed serial data transfer can be achieved, but the system becomes unsuitable for cold environments due to power dissipation
Solution Approach 1:
The patent replaces CMOS electronic circuits with superconducting RQL circuits that operate at cryogenic temperatures. The receiver system uses superconducting Josephson junctions and flux quantum-based logic elements instead of CMOS transistors, enabling high-speed data transfer while maintaining compatibility with cold superconducting environments through fundamental substitution of the technological platform.
2Measurement precision
If PLL-based clock recovery is implemented, then accurate data sampling can be achieved, but the system complexity increases due to the absence of PLL functionality in RQL
Solution Approach 1:
The patent implements a digital clock recovery mechanism that copies and emulates PLL functionality through software-defined logic in the RQL receiver. The system uses a recovery clock generator that produces a clock signal synchronized to the incoming data stream by detecting transition edges and adjusting phase through digital control, replicating analog PLL behavior in a digital superconducting context without requiring physical PLL circuitry.
3Reliability
If oversampling is used to mitigate noise and jitter, then data integrity improves, but the processing complexity increases
Solution Approach 1:
The patent implements oversampling by taking multiple samples of each data bit at different time points within the bit period, before making the final data decision. The receiver samples the incoming serial data stream at a rate higher than the nominal data rate, captures multiple samples per bit, and then uses digital logic to determine the final data value, thereby mitigating noise and jitter effects through preliminary redundant sampling.
Data Source
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AI summary
One embodiment describes a reciprocal quantum logic (RQL) receiver system. The RQL system is configured to convert a serial input data stream provided from a serial data transmitter into an RQL data stream. The RQL receiver system includes a sampling controller configured to oversample the serial input data stream via a plurality of samples over each sampling window of an RQL clock signal to determine a transition sample corresponding to a transition in a digital value of the serial input data stream in a given one sampling window of the RQL clock signal. The RQL receiver system can be further configured to capture the digital value of the serial input data stream via a capture sample that is a predetermined number of samples subsequent to the transition sample in each sampling window of the RQL clock signal.