RR-RDIMM Redriving Circuits for Memory Bus Signal Isolation
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Solution Overview
Problem
Current memory modules, such as DIMMs and RDIMMs, face challenges in managing the increased loading on address, control, and data signals as the number of DRAM chips and modules grows, leading to uncertainty and potential bottlenecks in system memory bus operations, especially with the need for error correction and synchronization.
Innovation Solution
The redriven/retimed registered dual inline memory module (RR-RDIMM) incorporates address register circuits, timing and control circuits, and data redriving/retiming circuits to isolate and buffer signals, allowing for independent operation regardless of the number of DRAM chips, with a central RRR controller managing signal integrity and redundancy, enabling flexible configuration and self-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of DRAM chips and memory modules is increased to provide larger memory capacity, then the memory capacity is improved, but the loading on address, control, and data signals increases causing uncertainty and potential bottlenecks in system memory bus operations
Solution Approach 1:
The patent introduces redriving circuits as intermediary components between the memory controller and DRAM chips. These circuits act as signal regenerators that receive weakened signals from the memory controller, restore them to full strength, and forward them to the DRAM chips. This intermediary function allows the system to support more DRAM chips without proportionally increasing signal loading on the memory bus, as each redriver segment isolates and regenerates signals locally.
Solution Approach 2:
The memory module is segmented into multiple sections, each with its own redriving circuits. Instead of having all DRAM chips directly connected to the memory controller in a single large bus, the system divides the memory array into smaller segments connected through redriver stages. This segmentation reduces the effective loading on any single segment of the memory bus, allowing scalability to higher capacities while maintaining signal integrity.
2Reliability
If error correction and synchronization are implemented to improve reliability, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple functions into integrated circuits on the memory module. The redriving circuits are integrated with registration and error correction capabilities, consolidating what would otherwise be separate complex circuits into unified components. This merging approach maintains reliability through error correction while reducing overall device complexity compared to implementing each function separately.
Solution Approach 2:
The memory module incorporates self-testing and self-diagnosis capabilities through integrated circuits that can automatically detect and report errors. The system includes self-refresh functionality and automatic error correction without requiring external intervention, reducing the complexity of external control circuits while maintaining high reliability through autonomous operation.
Data Source
AI summary
A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.