RRAM Electrode Structure With Air Gap for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing RRAM structures face challenges with high parasitic capacitance and RC delay due to their formation in the back-end metallization process, which affects their performance.
Innovation Solution
A semiconductor memory device structure is developed with a substrate, dielectric layers, and electrodes, including a resistive-switching layer and an air gap, where the top electrode has a tapered upper portion and a lower portion, and a method for forming this structure is described, involving deposition and polishing steps to create specific layer configurations that reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RRAM structure is formed in the back-end metallization process, then device integration is achieved, but parasitic capacitance and RC delay increase
Solution Approach 1:
The patent introduces an air gap dimension in the vertical stacking configuration, creating a three-dimensional structure that separates capacitive coupling paths. The air gap physically isolates the bottom electrode from underlying structures, reducing parasitic capacitance while maintaining the integrated RRAM device architecture formed in the back-end metallization process.
Solution Approach 2:
The patent segments the dielectric layers into multiple distinct components: first dielectric layer, second dielectric layer, and third dielectric layer, with the air gap positioned between them. This segmentation allows independent optimization of each layer's function, particularly enabling the air gap to serve as a capacitive isolation element while other dielectric layers provide structural support and electrical insulation.
2Object-affected harmful factors
If top electrode has tapered upper portion and lower portion configuration, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The top electrode is designed with an asymmetric geometry featuring a lower portion with first width and an upper portion with second width that is greater than the first width. This asymmetric configuration optimizes the electrode's capacitive coupling characteristics, reducing parasitic capacitance by controlling the surface area distribution at different vertical positions while maintaining electrical functionality.
Solution Approach 2:
The patent utilizes parameter changes in the electrode geometry, specifically varying the width parameter from the lower portion to the upper portion of the top electrode. This parameter optimization reduces parasitic capacitance by controlling the effective surface area for capacitive coupling, achieving better electrical performance without requiring fundamentally new manufacturing processes.
Data Source
AI summary
A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.