RRAM Device Structure Using Amorphous Silicon for CMOS Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink below 100 nm, they face issues like short channel effects and high programming voltage leading to dielectric breakdown, and non-volatile memory devices such as Flash memories face challenges with material compatibility and scalability, reliability, and high power consumption.
Innovation Solution
The development of resistive switching devices using a substrate with a dielectric and wiring materials, incorporating a p+ polycrystalline silicon or p-doped silicon germanium junction material, and an amorphous silicon resistive switching material with intrinsic semiconductor characteristics, allowing for electric field-induced resistance changes and reduced contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced below 100 nm to continue scaling, then productivity and integration density are improved, but short channel effects and device operation reliability deteriorate
Solution Approach 1:
The patent changes the operational mechanism from field-effect based (FET) to resistive switching based, fundamentally altering the device physics to enable scaling below 100 nm while avoiding short channel effects that plague traditional FETs at these dimensions
Solution Approach 2:
The patent replaces the mechanical/electrical field control mechanism of FETs with an electrical resistance-based switching mechanism, where the state is determined by material resistance changes rather than field effect, enabling continued scaling
2Ease of operation
If high voltage is applied for programming Flash memories, then programming capability is achieved, but dielectric breakdown and device reliability deteriorate
Solution Approach 1:
The patent changes the programming mechanism from high-voltage charge injection to low-voltage resistive switching, where programming is achieved through controlled resistance changes in the switching material rather than high-voltage dielectric breakdown
Solution Approach 2:
The patent converts the harmful high-voltage stress that causes dielectric breakdown into a beneficial low-voltage resistive switching mechanism, where the switching material's resistance change is the desired effect rather than a failure mode
3Adaptability or versatility
If new materials are used for non-Flash memory devices (Fe-RAM, MRAM, ORAM), then memory functionality is achieved, but manufacturing compatibility and ease of manufacture deteriorate
Solution Approach 1:
The patent uses amorphous silicon, a material already widely used in CMOS technology, rather than introducing incompatible materials like organic chemicals for ORAM or high-temperature materials for Fe-RAM and MRAM, ensuring full manufacturing compatibility
Solution Approach 2:
The patent achieves multiple memory functionalities using standard CMOS-compatible materials and processes, making the technology universally manufacturable in existing foundries without requiring specialized equipment or processes
4Adaptability or versatility
If PCRAM switching mechanism is used, then memory functionality is achieved, but power consumption increases due to Joules heating
Solution Approach 1:
The patent changes the switching mechanism from Joules heating-based (PCRAM) to electric field-induced resistive switching, where the switching is achieved through field effect rather than thermal effects, dramatically reducing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable, scalable, and low-power non-volatile memory devices with improved data retention and reduced contamination, compatible with existing CMOS fabrication techniques.
Implementation Method 1
a resistive switching material comprising an amorphous silicon-bearing material having an intrinsic semiconductor characteristic
Data Source
AI summary
A method of forming a resistive device includes forming a first wiring layer overlying a first dielectric on top of a substrate, forming a junction material, patterning the first wiring layer and junction material to expose a portion of the first dielectric, forming a second dielectric over the patterned first wiring layer, forming an opening in the second dielectric to expose a portion of the junction material, forming a resistive switching material over the portion of the junction material in the opening, the resistive switching material having an intrinsic semiconductor characteristic, forming a conductive material over the resistive switching material, etching the conductive material and the resistive switching material to expose respective sidewalls of the resistive switching material and the conductive material, and the second dielectric, and forming a second wiring layer over the conductive material in contact with the respective sidewalls and the second dielectric.