RRAM Array Biasing Without Source Line Reset Stress
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Solution Overview
Problem
Conventional RRAM architectures require complex, area-consuming peripheral circuitry for selective voltage application, leading to poor performance and high bit error rates due to the use of high positive voltages and undue device stress.
Innovation Solution
An RRAM structure with continuously connected source lines to ground and zone-specific bit and word line biasing circuits that apply operation-dependent and connection-dependent voltages, eliminating the need for source line biasing and reducing voltage requirements, particularly during reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional RRAM architectures use complex peripheral circuitry for selective voltage application, then operation control is achieved, but area consumption increases and device stress increases
Solution Approach 1:
The patent extracts and eliminates the source line biasing circuitry from the conventional RRAM architecture. By removing this complex peripheral circuitry component, the design achieves simpler operation control without requiring additional area-consuming biasing circuits, directly resolving the contradiction between operational control capability and device complexity
Solution Approach 2:
The bit line is designed to serve multiple functions: it provides both the read/write signal path and the bias voltage for the RRAM cell. This multi-functional design eliminates the need for separate source line biasing circuits, reducing peripheral circuitry complexity while maintaining operation control capability
2Ease of operation
If high positive voltages are applied during reset operations, then reset function is achieved, but device stress increases and bit error rate increases
Solution Approach 1:
The patent inverts the conventional voltage application approach for reset operations. Instead of applying high positive voltages to both word line and bit line, the invention applies a negative voltage to the bit line while applying a lower positive voltage to the word line. This inverted voltage scheme reduces device stress and prevents the formation of conductive filaments that cause bit errors, while still achieving the reset function
Solution Approach 2:
The patent changes the voltage parameters during reset operations by introducing negative voltage on the bit line instead of high positive voltage. This parameter change (from high positive to negative) reduces the overall voltage stress on devices and eliminates the harmful effects associated with high positive voltage application, while maintaining the reset functionality
3Ease of operation
If high positive voltages are applied during forming and set operations, then write operations are achieved, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameters for forming and set operations by applying negative voltage to the bit line instead of high positive voltage. This parameter change reduces the power consumption during write operations while maintaining the ability to form and set conductive filaments in the RRAM cell, directly addressing the contradiction between operational capability and energy consumption
Data Source
AI summary
Disclosed are a resistive random access memory (RRAM) structure and operating method. The RRAM structure includes RRAM cells arranged in columns and rows with all cells in a column connected between source and bit lines for the column and with all cells in a row connected to a word line for the row. The RRAM structure also includes peripheral circuitry enabling all memory operations to be performed without selective source line biasing. For example, during a reset operation, the following voltage conditions can be applied: a low positive voltage (e.g., of +1.8V) to the word line of the row containing the selected RRAM cell; a low negative voltage (e.g., of −1.8V) to all other word lines; and another low negative voltage (e.g., of −1.6V) to the bit line of the column containing the selected RRAM cell. All source lines and all other bit lines can be discharged to ground.