Resistive Random Access Memory Array With Programmable Processing Elements
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Solution Overview
Problem
Current resistive-switching memory technologies face challenges in achieving high memory density and efficient processing power while minimizing power consumption, as they are still in the development stage and lack effective integration with existing semiconductor architectures.
Innovation Solution
A non-volatile memory architecture featuring a resistive random access memory array with multiple sets of bitlines and wordlines, incorporating programmable processing elements and read sense amps, which enables parallel data processing and error correction, and utilizes a dual interface system for optimized data transfer and bandwidth management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistive-switching memory technology is used to increase memory density, then memory capacity is improved, but power consumption increases and integration with existing semiconductor architectures becomes difficult
Solution Approach 1:
The memory array is divided into multiple banks, with each bank containing multiple arrays. This segmentation allows selective activation of only the necessary memory banks and arrays for each operation, reducing the overall power consumption while maintaining high memory density capacity.
Solution Approach 2:
The memory architecture implements dynamic power management through wordline selection mechanisms and sense amp activation only when needed. The system can dynamically adjust which memory arrays are active based on the specific data access requirements, optimizing the balance between memory density utilization and power consumption.
2Quantity of substance
If more semiconductor devices are fabricated on a given geometric area to increase memory capacity, then memory density is improved, but processing power and architectural integration become more complex
Solution Approach 1:
The memory architecture employs universal control signals and standardized interfaces that can operate across different memory banks and arrays. The sense amplifiers and decode circuits are designed to handle multiple arrays through common control logic, reducing the complexity of integrating high-density memory structures into the semiconductor architecture.
Solution Approach 2:
Sense amplifiers serve as intermediary components between the memory arrays and the external interface. These sense amps buffer and condition the signals from multiple memory arrays, allowing high-density array integration without proportionally increasing the complexity of the external interface and control logic.
3Ease of manufacture
If two-terminal memory devices are used to reduce device structure complexity, then manufacturing is simplified, but control precision and signal mediation capability are reduced
Solution Approach 1:
The architecture replaces the need for mechanical gate control structures with electrical field control through wordlines. The two-terminal memory devices are controlled by applying voltages to shared wordlines, which electrically modulate the conductivity of multiple memory cells simultaneously, achieving precise control without complex mechanical gate structures.
Solution Approach 2:
The memory array is segmented into multiple arrays sharing common wordlines and sense amplifiers. This segmentation allows the two-terminal devices to be controlled in groups through shared control lines, maintaining manufacturing simplicity while achieving precise conductivity control through coordinated activation of specific wordline-sense amp pairs.
Data Source
AI summary
Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.