RRAM Memory Structure With Reduced BEOL Step Height
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Solution Overview
Problem
As integrated chip components scale, the height of Resistive Random Access Memory (RRAM) devices within the back-end-of-the-line (BEOL) interconnect stack fails to reduce, leading to step height issues and process window problems between embedded memory and logic regions, affecting yield and reliability.
Innovation Solution
The RRAM device design eliminates the bottom electrode via, with a first interconnect via contacting the top electrode and a second via contacting the bottom electrode, reducing the device height to between 600 and 800 angstroms, thereby mitigating step height differences and process window issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RRAM device includes a bottom electrode via, then the device structure is complete and functional, but the device height becomes too large causing step height issues and process window problems
Solution Approach 1:
The patent removes the bottom electrode via from the traditional RRAM device structure, extracting the problematic element that caused excessive device height. This extraction eliminates the step height issues and process window problems while maintaining device functionality through alternative interconnect via configurations.
2Length of stationary object
If the RRAM device height is reduced to 600-800 angstroms, then step height differences and process window issues are mitigated, but the device structure becomes more complex with multiple interconnect vias
Solution Approach 1:
The patent transitions from a vertical via configuration to a lateral interconnect approach, where interconnect vias are positioned at the same level as the electrodes rather than extending through the device height. This dimensional change allows height reduction while managing complexity through planar integration.
3Length of stationary object
If the RRAM device height is reduced, then integration with adjacent logic regions is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates interconnect vias during the same fabrication process step as the electrodes, performing the via formation action preliminarily rather than as a separate subsequent step. This preliminary action reduces the need for additional high-precision alignment steps and simplifies manufacturing.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.