RRAM Cell Biasing for Concurrent Operations
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Solution Overview
Problem
Existing RRAM cell arrays require bipolar voltages for setting and resetting, complicating the design and making concurrent operations challenging, especially since negative voltage charge pumps are necessary, which complicates the design and requires changing biasing conditions for reading and writing.
Innovation Solution
A biasing technique that uses non-negative voltages for RRAM cells, allowing concurrent setting and resetting of cells on the same word line without negative voltages, by employing bit line control circuits that generate command voltages and currents to manage the states of RRAM cells using a static bias voltage greater than the minimum negative voltage required for the RESET state, enabling concurrent memory operations without changing biasing conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bipolar voltages are used to set and reset RRAM cells, then the RRAM cells can be placed in specific states (SET and RESET), but the design becomes complicated and negative voltage charge pumps are required
Solution Approach 1:
The patent extracts and eliminates the negative voltage charge pump from the system by using a modified cell structure with a transistor and source line biasing. This allows SET and RESET operations to be performed using only non-negative voltages on the bit line, removing the complex negative voltage generation circuitry while maintaining reliable RRAM cell state control
Solution Approach 2:
The patent changes the voltage parameter constraints by introducing a static bias voltage on the source line. This allows the bit line voltage to be clamped between Vbias and Vbias+Vset-max, enabling all operations (SET, RESET, READ) to be performed with non-negative voltages while maintaining proper cell state transitions
2Reliability
If negative voltages are required for RESET operations, then RRAM cells can be reset to high resistance state, but concurrent setting and resetting of cells on the same word line becomes challenging
Solution Approach 1:
The patent segments the voltage control functions between the bit line and source line. The bit line handles dynamic voltage changes for SET/RESET/READ operations, while the source line provides a static bias voltage. This segmentation allows different operations to proceed concurrently on the same word line by independently controlling bit line voltages for different cell columns
Solution Approach 2:
The patent applies preliminary action by pre-biasing the source line to a static voltage Vbias before any bit line operations. This preliminary biasing establishes the voltage reference that enables subsequent SET and RESET operations to be performed with non-negative bit line voltages, allowing concurrent operations without waiting for voltage transitions
3Reliability
If biasing conditions are changed for reading and writing operations, then proper voltage levels can be applied to RRAM cells, but the design becomes more complex and operations are slower
Solution Approach 1:
The patent makes the source line bias voltage universal, serving multiple functions: it enables SET operations, RESET operations, and READ operations all with non-negative voltages. This single static bias voltage replaces the need for different biasing conditions for different operations, simplifying the design while maintaining voltage level accuracy for all cell operations
Data Source
AI summary
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.