RRAM Bit Line Segmentation for Reset Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive random-access memory (RRAM) devices face high reset currents and prolonged reset times, leading to inefficiencies in power consumption during the reset procedure of memory cells.
Innovation Solution
The RRAM device architecture includes parallelly arranged word lines, bit lines, and source lines, where each bit cell comprises a transistor and a resistive element, allowing for selective reset of bit cells by applying voltage logic levels to reduce unnecessary pre-charging of bit lines, thereby minimizing reset current and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are pre-charged to reset certain memory cells, then the reset operation can be performed, but huge currents are consumed
Solution Approach 1:
The patent divides the bit lines into multiple groups, where each group is associated with a specific word line. Only the bit lines in the group corresponding to the selected word line are pre-charged during reset operations, rather than pre-charging all bit lines. This segmentation approach reduces the number of bit lines requiring pre-charge, thereby reducing reset current consumption while maintaining reliable reset functionality for the targeted memory cells.
2Reliability
If all bit lines are pre-charged to reset memory cells, then the reset operation can be completed, but the reset time is prolonged
Solution Approach 1:
By segmenting bit lines into groups associated with specific word lines, the patent enables selective pre-charging of only those bit lines that need to be charged for the current reset operation. This reduces the total time required for pre-charging compared to charging all bit lines, thereby reducing reset time while ensuring reliable reset operation for the intended memory cells.
3Reliability
If conventional RRAM device architecture is used, then memory cells can be reset, but power efficiency is reduced due to high reset current
Solution Approach 1:
The patent implements segmentation of bit lines into multiple groups, each associated with a specific word line. During reset operations, only the bit lines in the relevant group are pre-charged, significantly reducing the total current required compared to conventional architectures that pre-charge all bit lines. This segmentation strategy maintains reliable reset functionality while improving power efficiency by reducing energy loss during reset operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces reset current and time, enhancing power efficiency and enabling concurrent set and reset operations across different bit cells, improving overall performance.
Implementation Method 1
RRAM devices operate by a principle that a dielectric, which is normally non-conductive, can be made conductive through a filament or conduction path formed after the application of a sufficiently high voltage
Implementation Method 2
The conduction path formation can arise from different mechanisms, including defects, metal migration, and other mechanisms
Implementation Method 3
The dielectric element may be reset to the non-conductive state or a high resistance state, or set to the conductive state or a low resistance state, by applying an appropriately voltage
Data Source
AI summary
A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines.