RRAM Cell Bottom Electrode Spacer Design

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Solution Overview

Problem

The performance of resistive random access memory (RRAM) cells is limited by the width of the bottom electrode, which affects switch efficiency and reliability, as existing manufacturing processes cannot produce electrodes narrower than their photolithography dimension limitations.

Innovation Solution

The RRAM cell design incorporates a narrow bottom electrode surrounded by a spacer and a bottom dielectric layer, allowing for a width smaller than the manufacturing process limitations, which improves data retention and endurance by forming a triangular filament region for faster and more sensitive set and reset operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bottom electrode width is reduced to improve switch efficiency and reliability, then the retention and endurance performance improves, but the manufacturing process cannot produce electrodes narrower than its photolithography dimension limitations

Engineering Contradiction:
Improveswitch efficiency and reliabilityVSAvoidelectrode width
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The bottom electrode structure is segmented into multiple functional regions: a narrow active electrode region for switching and wider contact regions for manufacturing. This segmentation allows the critical switching region to be narrow enough for high performance while the contact regions accommodate manufacturing tolerances.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the bottom electrode structure are given different widths and functions. The central active region has a narrow width optimized for switching performance, while the contact regions have wider dimensions for reliable electrical connection, allowing each region to be optimized for its specific function.

Inventive Principle:
Principle #3Local quality

2Speed

If the bottom electrode width is reduced to form a triangular filament region for faster switching, then the set and reset operation speed improves, but the manufacturing precision limitation prevents achieving the required narrow dimensions

Engineering Contradiction:
Improveset and reset operation speedVSAvoidelectrode width
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The spacer structure is formed first to define the narrow region boundaries, then the bottom electrode material is deposited conformally. This preliminary formation of the spacer framework allows the subsequent electrode deposition to achieve narrow dimensions that would be impossible with direct photolithography patterning.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer acts as an intermediary structure that enables the formation of narrow electrode regions. By using the spacer as a template and barrier, the manufacturing process can achieve dimensions smaller than the photolithography resolution limit through conformal deposition techniques.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9209392B1RRAM cell with bottom electrode
Publication Date: 2015.12.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9209392B1 patent drawing
  • US9209392B1 patent drawing
  • US9209392B1 patent drawing

AI summary

The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.