RRAM Cap Layer Stress Gradient for Lower Forming Energy

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Solution Overview

Problem

Resistive random access memory (RRAM) cells face challenges in reducing the energy required for the forming step and improving the quality of the resistance random access memory, as the stress of the cap layer covering the RRAM body changes during the forming process, affecting the lattice arrangement and carrier migration.

Innovation Solution

Ion doping is performed on the cap layer to create a stress gradient with different stresses in the upper and lower halves, reducing the energy needed for the forming step and enhancing the carrier migration rate by adjusting the lattice arrangement before the forming process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If ion doping is performed on the cap layer to create a stress gradient, then the energy required for the forming step is reduced and carrier migration rate is accelerated, but the device complexity and manufacturing process complexity increase

Engineering Contradiction:
Improveenergy required for forming stepVSAvoidmanufacturing process complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Ion doping is performed on the cap layer before the forming step to pre-establish a stress gradient that facilitates subsequent carrier migration. This preliminary action prepares the lattice structure in advance, reducing the energy needed during the actual forming operation and accelerating carrier migration rates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The stress state of the cap layer is changed from uniform to gradient distribution through controlled ion doping. By modifying the stress parameter spatially across the cap layer thickness, the lattice arrangement is optimized to reduce forming energy and enhance carrier migration without fundamentally changing the device architecture.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If a uniform stress cap layer is used, then the manufacturing process is simpler, but the lattice arrangement does not optimize carrier migration and higher forming energy is required

Engineering Contradiction:
Improvecap layer fabrication simplicityVSAvoidcarrier migration efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The cap layer is designed with non-uniform stress distribution, where different regions (upper half vs lower half) have different stress states. This local quality variation creates optimal lattice arrangements in specific regions to enhance carrier migration efficiency, while the overall structure remains a single continuous layer for manufacturing simplicity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress gradient in the cap layer reduces the energy required for the forming step and improves the quality of the RRAM by optimizing the lattice arrangement and carrier migration, leading to better performance characteristics.

Implementation Method 1

ion doping is carried out on the cap layer covered outside the resistance random access memory to form a stress gradient inside the cap layer

Methodology Applied
Scientific EffectIon doping: Ion Implantation

Data Source

PatentUS11793091B2Semiconductor structure and manufacturing method thereof
Publication Date: 2023.10.17 UNITED MICROELECTRONICS CORP
  • US11793091B2 patent drawing
  • US11793091B2 patent drawing
  • US11793091B2 patent drawing

AI summary

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.