RRAM Capacitor Structure Seam Leakage Prevention
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Solution Overview
Problem
Resistive random access memory (RRAM) devices face challenges with leakage issues due to the formation of seams during the deposition of conductive layers, which affect production yield and cost.
Innovation Solution
A memory device structure is developed with a capacitor structure that includes a bottom electrode, a variable resistance layer, and a top electrode, where a second dielectric layer with a smaller aspect ratio is used to avoid contact with seams, and a conductive layer is formed with a flat surface to prevent leakage, using techniques like chemical vapor deposition and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conductive layer is deposited to form RRAM devices, then the memory device structure is formed, but seams are created during deposition which cause leakage issues
Solution Approach 1:
A planarization layer is formed over the conductive layer before subsequent processing steps. This preliminary action creates a flat surface that prevents seams from affecting the capacitor structure formation and eliminates leakage paths, while maintaining the ease of conductive layer deposition.
2Reliability
If the conductive layer is formed with high precision to avoid seams, then leakage is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
A planarization layer is introduced as an intermediary element between the conductive layer and the capacitor structure. This intermediate layer absorbs the surface irregularities and seams, allowing the conductive layer to be formed with standard precision while still achieving leakage-free operation.
3Reliability
If the aspect ratio of openings is reduced to avoid seams, then leakage is prevented, but the area and volume of the device increase
Solution Approach 1:
The planarization layer is formed in advance to create a flat surface, allowing subsequent capacitor structures to be formed with standard aspect ratios. This preliminary flattening action prevents seam formation without requiring reduced aspect ratios, thereby maintaining compact device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the risk of leakage in RRAM devices, improves production yield, and decreases costs by eliminating seams and enhancing the flatness of the conductive layer, thereby improving the reliability and efficiency of the memory device.
Implementation Method 1
using techniques like chemical vapor deposition and chemical mechanical polishing
Implementation Method 2
using techniques like chemical vapor deposition and chemical mechanical polishing
Data Source
AI summary
Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.