RRAM Cell Fabrication via Selective Etching
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Solution Overview
Problem
Current semiconductor transistor-based memory technologies face limitations in performance, reliability, and density, prompting the need for alternative two-terminal memory devices like resistive random access memory (RRAM) cells that offer improved write, erase, and access times, as well as higher memory density.
Innovation Solution
The development of a resistive random access memory (RRAM) cell using a multilayered structure with a bottom electrode, dielectric material, switching matrix, barrier material, and dielectric hardmask, patterned through a three-step selective subtractive etching process to efficiently form the memory device without damaging the layers, employing plasma etching and ion milling to achieve precise patterning and minimize material redeposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-terminal semiconductor transistors are used for memory devices, then device structure and control are well-established, but memory density and performance are limited
Solution Approach 1:
The patent extracts the control functionality from the three-terminal transistor structure and integrates it into the two-terminal RRAM device itself, eliminating the need for separate access transistors. This extraction enables higher memory density while maintaining reliable write and read operations through the inherent resistive switching behavior of the RRAM cell.
Solution Approach 2:
The patent inverts the conventional memory architecture by using the RRAM cell as both the storage element and the access element. Instead of using transistors to control RRAM cells, the design allows direct addressing of RRAM cells through shared bitlines and wordlines, fundamentally changing the control mechanism from three-terminal to two-terminal operation.
2Manufacturing precision
If conventional etching processes are used for patterning, then manufacturing is simpler, but layer damage and material redeposition occur
Solution Approach 1:
The patent segments the etching process into three distinct steps with different etchants and parameters: first etching the dielectric hardmask, second etching the barrier material, and third etching the switching matrix. Each step is optimized for its specific layer, achieving precise patterning while preventing damage to underlying layers and minimizing material redeposition.
Solution Approach 2:
The patent changes multiple parameters across the three etching steps including etchant chemistry, power density, pressure, and gas composition. These parameter changes enable selective removal of different materials with high precision while controlling the etching profile to prevent sidewall damage and reduce redeposition of etched materials.
3Quantity of substance
If memory density is increased, then storage capacity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by optimizing each etching step for its specific target layer with tailored etchants and parameters. The first step targets the dielectric hardmask with one set of conditions, the second targets the barrier material with different conditions, and the third targets the switching matrix with yet another set of conditions, enabling precise patterning at high density.
Solution Approach 2:
The patent performs preliminary patterning of the dielectric hardmask before etching the underlying barrier material and switching matrix. This sequential approach establishes precise boundaries early in the process, guiding subsequent etching steps to achieve the required patterning precision for high-density memory structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient fabrication of RRAM cells with enhanced memory density, faster programming speeds, and reduced manufacturing costs, while maintaining data integrity and non-volatility, overcoming the limitations of traditional semiconductor memory technologies.
Implementation Method 1
employing plasma etching and ion milling to achieve precise patterning
Implementation Method 2
employing plasma etching and ion milling to achieve precise patterning and minimize material redeposition
Data Source
AI summary
A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.